Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-06-08
2002-03-26
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185200, C365S189090, C365S207000
Reexamination Certificate
active
06363015
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a reading method for non-volatile memory cells with a sensing ratio depending on the reading voltage and to a device to realize said method.
2. Discussion of the Related Art
Semiconductor memories are universally organized as arrays having cells of the capacitance of a single bit. These arrays are surrounded by an address decoding logic and by circuitry for interfacing with outside signals.
As known, the largest part of the memories works in a way that the row address enables all the cells along the selected line. The contents of these cells become available along the selected column line.
Additional circuitry, including sense amplifiers, control logic and input-output tri-state buffer is usually required to realize the functionality of the memory.
In memory devices like ROM (read only memory), EPROM (erasable programmable ROM), EEPROM (electrically erasable programmable ROM), etc. the reading of said memory cells occurs through the comparison of the current of the matrix cell (Ic) with a k fraction (with 0<k<1) of the current of a reference cell (Ir), that is technologically identical to the matrix cell. In said types of devices single ended sense amplifiers are usually used to perform reading and programming operation. The value of the current in the programmed memory cell must be lower than a k fraction of the value of the current of the reference memory cell, that is Icp<k*Ir. The value of the current in a virgin memory cell must be higher than a fraction of the current of the memory reference cell, that is Icv>k*Ir.
For the programmed cells a high sensing ratio k would be preferable to make necessary a lower jump of the threshold level in function of the maximum reading voltage, so as to allow a higher maximum reading voltage. For the virgin cells a low sensing ratio would be preferable because, when the reading operation happens with values of voltage near the values of the threshold voltage of the cell, a low k facilitates this kind of operation. The k ratio is called the sensing ratio and is determined by technological considerations, as the level of the threshold voltage of the virgin cell and the possible threshold jump after a programming operation, and by device features, like the supply voltage. Such choice constitutes a compromise between two contrasting demands.
Usually, in a typical sense amplifier with fixed current unbalance, a cell of the matrix memory is selected by the row decoder and by the column multiplexer and after a first preload and equalization operation of the two branches, one of which assigned to the transport of the current of the memory cell and the other to the transport of the current in the reference cell, the voltages that develop at the positive and negative terminal of the operational amplifier depend on the currents of the said two cells and on the transconductances of the transistors acting as loads. Therefore the sensing ratio k is in function of the transconductance ratio of the two load transistors and it results to be constant.
In view of the described state of the art, object of the present invention is to realize a system for reading the memory cells with a sensing ratio depending on the reading voltage.
SUMMARY OF THE INVENTION
In accordance with the present invention, this and other objects are achieved by a reading method for non-volatile memory cells comprising a first step in which a memory cell of the matrix is selected by the row decoder and the column multiplexer, a second step of preload and equalization during which the voltage on the drain electrode of the selected memory cell reaches a predefined value, and a third step during which the selected cell with a sensing ratio depending on the reading voltage of said cell is read.
According to another embodiment of the invention, a device is provided comprising at least a reference branch with at least one load transistor and a reading branch for reading the programmed memory cell and including at least one load transistor, including at least one modulation branch with at least one selection transistor and a load generator associated with said modulation transistor to modulate in an analogous way the transconductance of one of the two load transistors as a function of the reading voltage of the memory cell.
Thanks to the present invention it is possible to realize a reading system for the memory cells which has a sensing ratio k that varies as a function of the reading voltage of the memory cell.
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European Search Report from European Patent Application 99830382.0, filed Jun. 21, 1999.
Barcella Antonio
Rolandi Paolo
Auduong Gene N.
Morris James H.
STMicroelectronics S.r.l.
Wolf Greenfield & Sacks P.C.
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