Reading method and circuit for a non-volatile memory

Details Reading method and circuit for a non-volatile memory Reading method and circuit for a non-volatile memory

2000-10-27

2002-10-29

Elms, Richard (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185030, C365S185200

Reexamination Certificate

active

06473340

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a reading method and a circuit for a nonvolatile memory.
BACKGROUND OF THE INVENTION
As is known, in a floating gate non-volatile memory cell storage of a logic state is carried out by programming the threshold voltage of the cell itself through the definition of the quantity of electrical charge stored in the floating gate region.
Reading of a memory cell is carried out using a read circuit known as “sense amplifier,” which, in addition to recognizing the logic state stored in the memory cell, also provides for the correct biasing of the drain terminal of the memory cell.
FIG. 1
illustrates by way of example a known sense amplifier used to read multi-level flash memory cells.
The sense amplifier, indicated as a whole by
1
, is a successive approximation sense amplifier comprising a supply line
2
set to the supply voltage V
CC
; a ground line
4
set to the ground voltage V
GND
; an array branch
6
connected via an array bit line
8
to a non-volatile memory cell
10
, the content of which is to be read; a reference branch
12
connected via a reference bit line
14
to a digital/analog converter (DAC)
16
, which draws at an output a reference current I
R
; a current/voltage converter stage
18
connected to the array and reference branches
6
,
12
for converting the currents flowing in these branches respectively into an array potential V
M
and a reference potential V
R
; a differential comparator stage
20
for comparing the array and reference potentials V
M
and V
R
and supplying at an output a logic comparison signal COMP indicative of the result of the comparison; and an n-bit successive approximation register (SAR)
22
, wherein n is the number of bits stored in the memory cell
10
, having an input connected to the output of the comparator stage
20
, and a plurality n of outputs connected to respective inputs of the digital/analogue converter
16
, for driving the digital/analogue converter
16
in order to vary the reference current I
R
required by the converter at the output, in the manner described in detail hereinafter.
In the example illustrated, the memory cell
10
to be read is a multi-level memory cell in which four bits (16 levels) are stored, and has a gate terminal receiving a reading signal V
READ
, a drain terminal connected to the array bit line
8
, and a source terminal connected to the ground line
4
.
In the example illustrated, the successive approximation register
22
is consequently a four-bit register, and has four outputs, each of which is associated with a respective bit, and at which it supplies four control signals, indicated as B
3
, B
2
, B
1
and B
0
, assuming a logic level correlated to the logic value assumed by the corresponding bit.
The array branch
6
comprises an array biasing stage
24
for biasing the drain terminal of the memory cell
10
to a predetermined potential, typically 1V; and an array column decoding stage, for the sake of simplicity schematized in
FIG. 1
by means of a switch
25
, arranged between the array biasing stage
24
and the array bit line
8
, and typically formed of three series-connected NMOS transistors (not shown) receiving respective column decoding signals at gate terminals.
In particular, the array biasing stage
24
has a negative feedback cascode structure formed of a NMOS transistor
26
and a logic inverter
28
; the NMOS transistor
26
has a drain terminal connected to the current/voltage converter stage
18
, a source terminal connected to the array bit line
8
and to the input terminal of the logic inverter
28
, and a gate terminal connected to the output terminal of the logic inverter
28
. With this configuration, the electrical potential of the drain terminal of the memory cell
10
is approximately equivalent to the threshold voltage of the logic inverter
28
, at which potential, in other words, the logic inverter
28
switches from one logic level to the other.
The reference branch
12
comprises a reference biasing stage
30
altogether identical to the array biasing stage
24
, and having a feedback cascode structure formed of an NMOS transistor
32
and a logic inverter
34
; the NMOS transistor
32
has a drain terminal connected to the current/voltage converter stage
18
, a source terminal connected to the reference bit line
14
and to the input terminal of the logic inverter
34
, and a gate terminal connected to the output terminal of the logic inverter
34
.
The reference branch
12
additionally comprises a reference column decoding stage (not shown), arranged between the reference biasing stage
30
and the reference bit line
14
, formed of three series-connected NMOS transistors kept continually switched on (typically by connecting their gate terminals to the supply line
2
), and having the purpose of making the structure of the reference branch
12
and the array branch
6
symmetrical with one another.
The current/voltage converter stage
18
is formed of a current mirror comprising a first diode-connected PMOS transistor
36
arranged on the array branch
6
, and a second PMOS transistor
38
arranged on the reference branch
12
; in particular, the PMOS transistors
36
and
38
have gate terminals connected to one another and to the drain terminal of the PMOS transistor
36
, source terminals connected to the supply line
2
, and drain terminals connected respectively to the drain terminals of the NMOS transistor
26
and the NMOS transistor
32
, and defining respectively an array node
40
and a reference node
42
, at which the aforementioned array potential V
M
and reference potential V
R
, respectively, are present and to which the two input terminals of the comparator stage
20
are connected.
The sense amplifier
1
operates as follows. When a constant reading voltage V
READ
, having a value greater than the highest threshold voltage which can be programmed in the memory cell
10
, is applied to the gate terminal of the memory cell
10
, and provided that the drain terminal of the memory cell
10
is kept at a sufficiently low, constant value of approximately 1 V, the memory cell
10
works in the triode operating zone, and draws an array current I
M
which is inversely proportional to the threshold voltage programmed, i.e., the higher its threshold voltage, the lower the current flowing in it.
The array current I
M
is mirrored onto the reference node
42
by the PMOS transistors
36
and
38
of the current mirror
18
, and in the reference node
42
the reference current I
R
drawn by the digital/analogue converter
16
is subtracted from this mirrored current.
The array potential V
M
and the reference potential V
R
of the array node
40
and the reference node
42
, respectively, are thus correlated respectively to the array current I
M
, and to the difference between the reference current I
R
and the array current I
M
mirrored onto the reference branch
12
, and these potentials are compared with one another by the comparator stage
20
, which supplies at an output the comparison signal COMP, which assumes a first logic level if V
M
is greater than V
R
, and a second, low logic level, if V
M
is smaller than V
R
.
The comparison signal COMP is then supplied to the successive approximation register
22
, which, on the basis of the logic level of this signal, modifies the logic level of the control signals B
3
-B
0
, by implementing a dichotomous algorithm, which is known and therefore described briefly hereinafter.
In particular, the successive approximation register
22
controls the digital/analogue converter
16
such as to vary by steps the reference current I
R
drawn by the converter on the basis of the logic level assumed by the comparison signal COMP. In detail, as soon as the gate terminal of the memory cell
10
is supplied with the reading signal V
READ
, the successive approximation register
22
is controlled such as to set the control signal B
3
to the high logic level (most significant bit set to “1”). Consequently, the digital/analogue converter
16
draws a reference

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