Reading circuit for semiconductor non-volatile memories

Details Reading circuit for semiconductor non-volatile memories Reading circuit for semiconductor non-volatile memories

2001-09-13

2003-05-13

Lam, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185200, C365S189070

Reexamination Certificate

active

06563737

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a reading circuit for semiconductor non-volatile memories.
More specifically, the invention relates to a reading circuit for semiconductor non-volatile memories connected to at least one selected cell and to at least one reference cell, comprising current/voltage conversion circuits receiving at the input thereof a first current flowing through the selected cell and a second current flowing through the reference cell and providing respectively on a first circuit node a first selected cell voltage and on a second node a second reference cell voltage, as well as at least one differential amplifier, connected at the input of said first and second nodes and having an output terminal effective to supply the information stored in said selected cell.
The invention relates particularly, but non-exclusively, to a reading circuit for semiconductor non-volatile memories suitable for digital applications and implemented in CMOS technology, and the following description is given with reference to this field of application for convenience of illustration.
In particular, said circuit can be used both in conventional memories in which each memory element, or “memory cell”, stores an information bit (generally referred to as “two-level memories”) and in memories in which each memory element is capable to store more than one bit (generally referred to as “multilevel memories”).
Moreover, the circuit according to the invention can be used for information reading in non-volatile memories of the Flash, EPROM, EEPROM and OTP (One-Time Programmable) type.
2. Description of the Related Art
As is well known, a semiconductor non-volatile memory is a quite complex system. For example, as schematically shown in
FIG. 1
, a Flash memory
1
, i.e., a memory whose cells are electrically programmable and erasable in great bulks, generally referred to as blocks or sectors, conventionally comprises:
a cell matrix
2
, representing memory
1
core;
a decoding section, required to address the cells of the word to be selected during a particular programming or reading operation, as well as the sector or sectors to be erased during a particular erasing operation, and comprising essentially a line decoder
3
and a column decoder
4
, both connected to said cell matrix
2
;
a reading section, which performs the reading of the addressed cells and transmits the read data to output circuits, as well as an input/output section, which serves as interface for the insertion from the outside of the data to be stored in the addressed cells during a writing operation and for the transfer to the outside of the data concerning the read cells: said sections are schematically shown in
FIG. 1
by means of a sense amplifier
5
, regulators
6
connected to line decoders
3
and column decoders
4
, and at least one output buffer
7
connected to said sense amplifier
5
; and finally,
a supporting section comprising the circuits required to perform the above-described operations such as, for example, voltage step-up circuits
8
for generating the voltages required for performing programming and erasing operations in one-supply memories and connected to said regulators
6
, a state machine for an appropriate timing of the various operations (not shown).
It is also worth noting that an EPROM memory is a quite complex system, even though less complex than a Flash memory since it does not comprise some of the above-mentioned blocks (such as, for example, voltage step-up circuits
8
and matrix cell erasing circuits, erasing being performed in this type of memories through ultraviolet ray exposure). Therefore, the comments made with reference to Flash memories apply also to EPROM memories.
It is worth remembering that the information storage, in the case of conventional two-level memory cells, corresponds to the conduction or shutdown state of a floating gate transistor, which are associated with the logic values “1” and “0”. The two-level memory cell threshold voltage is high (Vthp) or low (Vthe) depending on the stored state, i.e., the charge stored in the floating gate terminal.
By using a greater number of charge values to be stored in the floating gate terminal than the two above-mentioned high and low threshold values, it is possible to increase the storage capacity, given the same cell size and technology. This is the case of “multilevel” cells.
More particularly, by using, for example, four different charge levels, corresponding to four different floating gate transistor conduction states, two bits can thus be coded in one cell, doubling therefore the cell information content, given the same area covered by the cell and thus by the whole memory.
Multilevel cells are generally inserted in a NOR-type architecture, so that a state stored in a cell is effective to inhibit the floating gate transistor conduction included therein during a reading operation, as is the case with “0” programmed cells in two-level cell devices, the remaining states being such as to provide different conduction conditions of the selected cell.
In the above-mentioned case of four programmable levels (two bits per cell) the cell threshold voltage can have one of the four possible values Vth
0
, Vth
1
, Vth
2
, Vth
3
, a two-bit binary configuration corresponding to each value.
The advantages in terms of storage capacity provided by a multilevel cell memory are however accompanied by considerable problems. These problems are mainly due to the reduced difference between the different memory cell conduction levels, i.e., between the threshold voltages corresponding to the different charge levels which can be stored in the floating gate terminal of the transistors included in the memory cells.
Said reduced difference between the threshold voltage levels involves serious problems in terms both of design (for example of programming and reading circuits) and of reliability of the whole memory device.
More particularly, in known memory devices, the reading circuit (essentially a sense amplifier), performs the fundamental function of comparing two current values, the one delivered by a selected cell and the other by the corresponding reference cell, and of outputting a voltage level corresponding to said comparison result. In a two-level cell, sensing margins, considered as the lowest current difference detectable at the sense amplifier inputs, are conveniently relaxed and the current comparison is performed without endangering the reading speed. In the case of four-level cells, the allocation of the different state distributions imposes more severe requirements on the reading circuit design than in the conventional two-level cell case.
The multilevel cell reading circuits are therefore more constrained by the need for high sensitivity, in order to discriminate very small signal differences at the inputs thereof. This feature poses specific design problems linked to the need for accuracy and, moreover, it does not meet the high speed requirement of the reading circuit sense amplifier.
More particularly, the sense amplifier must necessarily be highly sensitive, without endangering the reading speed. In fact, the sense amplifier sensitivity must be lower than the minimum distance in current between the level distribution and the adjacent references thereto.
If a read path is considered, the information supplied by the sense amplifier, which performs, as above described, the function of showing the content of the addressed cell it refers to, is generally stored in a register or “latch” which drives the driving circuit or output buffer (“data output buffer”), which performs the function of delivering the read data to external circuitries, which, according to the output buffer, can be modeled into a generally heavy capacitive load. The latch is generally used to keep the output buffer driving level constant for a predetermined period of time in order to make the output data transfer safe and reliable. The time instant for storing the information supplied by the sense amplifier must c

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