Reading circuit for semiconductor memory

Details Reading circuit for semiconductor memory Reading circuit for semiconductor memory

1992-09-29

1993-12-07

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Sync/clocking

36518906, G11C 800

Patent

active

052688747

ABSTRACT:
In a reading circuit for a semiconductor memory, connection between a bit line pair 3 and input line of a differential amplifier 4 is controlled using an address transition detection signal LTD. For equalizing the bit line pair 3 in pulse form after transition, the bit line pair 3 is connected to the input terminal of the differential amplifier 4 for a little longer period than the equalizing period, and for clamping the bit line pair 3, the bit line pair 3 and the input terminal of the differential amplifier 4 are disconnected from each other, thus allowing a high-speed, stable reading operation with large-scale capacity.

REFERENCES:
patent: 4730279 (1988-03-01), Ohtani
patent: 4926384 (1990-05-01), Roy
F. Miyaji et al., "A 25ns 4Mb CMOS SRAM with Dynamic Bit Line Loads", 1989 IEEE International Solid-State Circuits Conference, pp. 250-251, Feb. 17, 1989.

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