Reading circuit for nonvolatile memory cells without...

Details Reading circuit for nonvolatile memory cells without... Reading circuit for nonvolatile memory cells without...

2000-04-11

2001-11-27

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185200

Reexamination Certificate

active

06324098

ABSTRACT:

TECHNICAL FIELD
The present invention refers to a reading circuit for nonvolatile memory cells without limitation of the supply voltage.
BACKGROUND OF THE INVENTION
As is known, the design of circuits for reading nonvolatile memory cells is currently affected by different factors, which are often in competition with one another. In particular, these circuits must be able to work effectively with supply voltages that vary within a wide range of values. In fact, reading circuits must be compatible with supply voltages that are very low (for example, 2.5 V), necessary for minimizing energy consumption, but, at the same time, they must be able to work with high supply voltages in order to guarantee fast access times (lower than 100 ns). In addition, they should have overall dimensions as reduced as possible in order to favor large scale integration.
A further constraint is represented by the fact that present fabrication technologies do not enable perfectly identical cell arrays to be made, but, in particular, there exists a dispersion of the values of the threshold voltages with respect to a nominal value. Consequently, in a memory array, the most erased cells will have a threshold voltage slightly higher than 0.5 V, whilst the threshold voltage of the least erased cells will be approximately 2.5 V. Since generally the read voltage is equal to the supply voltage, the dispersion of the threshold voltages raises problems when the supply voltage is low (e.g., 2.5 V, as mentioned above). In this case, in fact, the least erased cells conduct a very low current and may be interpreted as written cells, thus causing reading errors. In addition, very low current levels require long reading times, which are unacceptable.
One solution for the described reading problems is given by European Patent Application EP-A-0 814 482 entitled “Method and Circuit for Generating a Reference Signal for Reading a Nonvolatile Memory”, filed on Jun. 18, 1996 in the name of the present applicant.
The above known solution will be described hereinafter for a better understanding of the problems met by the present invention, with reference to
FIGS. 1 and 2
, showing a reading circuit for nonvolatile memory cells and, respectively, plots of currents generated by this circuit. In
FIG. 1
, a reading circuit
1
comprises an array branch
2
, a reference branch
3
, a current-to-voltage converter
4
, and a biasing and decoding circuit
5
.
The array branch
2
in turn comprises a memory cell
7
, for example of the flash type, belonging to a memory array
6
and connected to an array bit line
9
and, with a gate terminal, to a charge pump
10
.
The charge pump
10
supplies an output voltage V
O
linked to the supply voltage V
DD
by the following relation:
V
O
=K
1
+V
DD
  (1)
where K
1
is a constant.
The reference branch
3
comprises a first NMOS transistor
13
, connected, with a drain terminal, via a reference line
14
, to the decoding and biasing circuit
5
and, with a gate terminal, to a second NMOS transistor
18
, diode connected, having its drain terminal connected to a reference generator
15
, which supplies at the output a current I
R
. The first NMOS transistor
13
and the second NMOS transistor
18
form a first current mirror circuit
11
and have equal shape factors (W/L)
G
, wherein W is the channel width and L is the channel length.
An array load
16
, including a PMOS transistor in diode configuration, and a reference load
17
, which belong to the current-to-voltage converter
4
, form a second current mirror circuit
19
and are connected, via the biasing and decoding circuit
5
, to the array bit line
9
and, respectively, to the reference line
14
.
In addition, the reference load
17
has a shape factor (W/L)
R
greater than the shape factor (W/L)
F
of the array load
16
. In particular, these shape factors are linked by the following relation:
(
W/L
)
R
=N
(
W/L
)
F
  (2)
where N is an integer, for example 8, representing the current amplification of the second current mirror circuit
19
.
Finally, a comparator
20
, having a first input and a second input connected, respectively, with the array load
16
and with the reference load
17
, has an output
21
, defining the output of the reading circuit
1
.
Operation of the device is as follows.
During reading, the reference current I
R
flowing in the second NMOS transistor
18
is mirrored in the first NMOS transistor
13
. As described in the European Patent Application referred to previously, the reference current I
R
is obtained as a linear combination of two currents I
1
and I
2
, carried by two reference cells not shown and having threshold voltages V
T1
and, respectively, V
T2
. In detail, the reference current I
R
is given by the following relation:
I
R
=(
I
1
−I
2
)+
NI
2
  (3)
where N is the same number as that appearing in Eq. (2).
Since the reference cells (not shown) in the reference generator
15
are biased so as to work in the linear region, approximate values of the currents I
1
and I
2
are given by the following expressions:
I
1
=G
(
V
GS1
−V
T1
)  (4)
I
2
=G
(
V
GS2
−V
T2
)  (5)
where V
GS1
and V
GS2
are the respective gate-to-source voltages of the reference cells, and G is their transconductance, which is constant. In addition, the gate-to-source voltages V
GS1
and V
GS2
, during reading, are equal to the supply voltage V
DD
of the reading circuit
1
.
Substituting Eq. (4) and Eq. (5) into Eq. (3) and setting V
GS1
=V
GS2
=V
DD
, the following relations are obtained:
I
R
=G
(
V
DD
−V
T1
)  (6a)
I
R
=G
(
V
DD
−V
T1
)−
G
(
V
DD
−V
T2
)+
NG
(
V
DD
−V
T2
)  (6b)
In particular, Eq. (6a) is valid for V
T1
<V
DD
<V
T2
, whilst Eq. (6b) is valid for V
DD
>V
T2
. As illustrated in
FIG. 2
, the plot of the reference current I
R
, expressed by relations (6a) and (6b) has a first rectilinear portion when the supply voltage V
DD
is between the threshold voltages V
T1
and V
T2
, and a second rectilinear portion, with a slope equal to NG, for values of V
DD
greater than V
T2
.
The reference current I
R
is compared with a current flowing in the reference load
17
, the value of which is determined by the current flowing in the memory cell
7
. In fact, the current I
F
flowing in the memory cell
7
and in the array load
16
is mirrored, amplified by a factor N, at the reference load
17
. In addition, the charge pump
10
supplies to the gate terminal of the memory cell
7
a voltage equal to the supply voltage V
DD
increased by a constant boosting voltage V
B
. As a result, if the memory cell
7
is written, the written cell current I
W
flowing in the reference load
17
is given by the following expression:
I
W
=NG
(
V
DD
+V
B
−V
TW
)  (7)
where V
TW
is the threshold voltage of a written cell. If, instead, the cell is erased, the erased cell current I
E
flowing in the reference load
17
is given by the following expression:
I
E
=NG
(
V
DD
+V
B
−V
TE
)  (8)
where V
TE
is the threshold voltage of an erased cell.
Expressions (7) and (8) may be rewritten as follows:
I
W
=NG[V
DD
−(
V
TW
−V
B
)]  (9)
I
E
=NG[V
DD
−(
V
TE
−V
B
)]  (10)
Consequently, the transcharacteristics I
W
−V
DD
and I
E
−V
DD
, given in
FIG. 2
, are similar to those of cells identical to the memory cell
7
, but having threshold voltages V
TW
−V
B
and V
TE
−V
B
, respectively. In particular, the written cell current I
W
and the reference current I
R
(for V
DD
>V
T2
) have parallel plots, with a slope equal to NG. This proves advantageous in so far as no top limit is set to the value of the supply voltage V
DD
, which can consequently be chosen so as to optimize the reading times.
Furthermore, when the reading circuit
1
is supplied with a low supply voltage V

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