Reading circuit for multilevel non volatile memory cell devices

Details Reading circuit for multilevel non volatile memory cell devices Reading circuit for multilevel non volatile memory cell devices

1997-06-04

1998-11-17

Nelms, David C.

Static information storage and retrieval

Floating gate

Multiple values

3651852, G11C 1134

Patent

active

058386122

ABSTRACT:
Reading circuit for multilevel non-volatile memory cell devices having, for each cell to be read, a selection line with which is associated a load and a decoupling and control stage with a feedback loop which stabilizes the voltage on a circuit node of the selection line. To this node are connected a current replica circuit which are controlled by the feedback loop. These include loads and circuit elements homologous to those associated with the selection line of the memory cell and have an output interface circuit for connection to current comparator circuit.

REFERENCES:
patent: 4833646 (1989-05-01), Turner
patent: 4967394 (1990-10-01), Minagawa et al.
patent: 5012448 (1991-04-01), Matsuoka et al.
patent: 5163021 (1992-11-01), Mehrotra et al.
patent: 5521865 (1996-05-01), Ohuchi et al.
IBM Technical Disclosure Bulletin, "Mid-Level Current Generator Circuit", vol. 33, No. 1B, Jun. 1990, pp. 386-388.

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