Reading circuit for a non-volatile memory

Details Reading circuit for a non-volatile memory Reading circuit for a non-volatile memory

2002-05-23

2003-12-23

Ho, Hoai (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185210

Reexamination Certificate

active

06667908

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to memory devices, and in particular, to a reading circuit for a non-volatile memory.
BACKGROUND OF THE INVENTION
The present invention relates to memory It is well known that to read a cell within a matrix of non-volatile memory cells, i.e., for determining whether a given cell is in one of two binary logic states, appropriate voltages have to be applied between the electrodes of that cell. The cells are arranged in rows and columns and are connected to each other by row and column conductors. These conductors, also respectively known as word lines and bit lines, make it possible for each individual cell to be biased for reading.
When a cell has been selected and biased in this manner, it can be read by a reading circuit that determines whether or not the appropriate column conductor (bit line) carries a current at that moment. A given cell of a memory of the EEPROM type (electrically erasable and programmable read-only memory) is conventionally considered to be programmed or in a logic state
1
when it carries a current, and erased or in a logic state
0
when it does not carry a current.
FIG. 1
schematically illustrates a known reading circuit, indicated overall by the reference number
10
. This reading circuit is as described, for example, in Italian Patent Application No. 1999000002119, filed on Oct. 11, 1999 and which is incorporated herein by reference in its entirety and is assigned to the assignee of the present invention.
The reading circuit
10
is associated with a matrix
11
of non-volatile memory cells interconnected by bit lines and word lines. A cell
12
is identified by the intersection of a bit line BL and a word line WL. Column decoding circuits
8
activate the bit lines one at a time. Row decoding circuits
9
activate the word lines one at a time. A memory cell is selected by applying appropriate voltages between its electrodes, and is then read by circuit
10
.
Each bit line has a parasitic capacitance indicated by C
BL,
which is the sum of the input capacitances of the column cells, the capacitance of the selection transistor of the column decoding circuit and the capacitance of the conductor that connects the gate electrodes of the column cells. The first task of the reading circuit
10
is to charge the bit line capacitance C
BL
. Only after the voltage applied to the capacitance C
BL
has exceeded a predetermined level will it become possible to read the selected cell.
Circuit
10
includes a detector for every bit line capable of sensing the current carried by the line. This detector comprises an N-channel MOS transistor, indicated by T
1
, that is connected to the bit line and to the positive pole VDD of a voltage source (whose negative pole, indicated by the ground symbol, is connected to the source electrodes of the matrix cells).
The source electrode of transistor T
1
is connected not only with the bit line BL, but also with the input of an inverter stage INV
1
that has its output connected to the gate electrode of the same transistor T
1
. The inverter stage INV
1
includes a pair of complementary MOS transistors, or more precisely, an N-channel MOS transistor TN
1
and a P-channel transistor TP
1
connected as shown in the drawing. The gate electrode of transistor TP
1
is connected to a constant-voltage source VP.
The reading circuit
10
also comprises a reference voltage generator
14
that comprises an N-channel MOS transistor T
0
and an inverter stage INV
0
made up of an N-channel MOS transistor TN
0
and a P-channel MOS transistor TP
0
. The transistors T
0
, TN
0
and TP
0
are connected to each other and to the external voltage sources VDD and VP in the same way as the transistors T
1
, TN
1
and TP
1
are connected. The reference voltage generator
14
also comprises a constant current generator G
0
that is connected between the source electrode of transistor T
0
and ground.
Using appropriate connections that are well known to a person skilled in the art, the reading terminal of the detector, i.e., the gate electrode of the transistor associated with each bit line, can be connected to an input terminal of a comparator
16
. For purposes of simplifying the figures, the gate electrode of the transistor T
1
and the electrode indicated in the drawing by MAT are connected directly to the input terminal of the comparator
16
. The gate electrode REF of the transistor T
0
is connected to another input terminal of the comparator
16
. The output terminal OUT of the comparator also forms the output of the reading circuit
10
.
Once the circuit is operating in steady conditions when a cell is selected for reading, such as cell
12
, for example, the current passing through the selected cell will also pass through the transistor T
1
. Since the transistor TN
1
is in a constant current biasing condition due to the constant voltage VP applied to the gate terminal of the transistor TP
1
, the gate electrode of the transistor T
1
, i.e., the node MAT, will be at a voltage level that depends on this current.
Voltage generator
14
operates in a manner that is similar to that of the current detector described above, but since the current of generator G
0
is constant, the gate electrode of transistor T
0
, i.e., the node REF, will remain at a constant voltage level. The components of generator
14
are dimensioned in such a manner that this constant voltage level will be between the two voltage levels that the node MAT can assume according to whether the associated cell is conducting or not.
Consequently, if the current passing through bit line BL is such that the voltage VMAT of the node MAT will be greater than reference voltage VREF on node REF, the output terminal OUT of comparator
16
will be in a first state corresponding to that of the programmed cell. Otherwise, the output terminal OUT will be in a second state corresponding to that of the non-programmed cell.
As already mentioned, the conditions described above refer to steady operating conditions. Let us now consider the dynamic behavior of the circuit during the reading. At the beginning of the reading the node MAT is substantially at the voltage VDD, the node TREF is substantially at a ground potential (zero), and the node BL likewise is at a ground potential because the capacitance C
BL
will be without a charge. At the beginning, the current passing through the transistor T
1
is only such as is necessary to charge the capacitance C
BL
. This is because the cell, even if it is programmed, i.e., capable of conducting, is not yet biased in such a way as to conduct because its drain voltage is too low.
In this initial phase there can occur critical operating conditions that may cause the voltage of the node MAT to be lower than it would be in steady conditions. This is due to the fact that transistor T
1
and inverter INV
1
are interconnected in such a way as to form a feedback loop that, even though it assures that the memory can be read very rapidly, may also create a transitory phenomenon that will cause the potential of node MAT to be smaller than its steady-condition value (undershooting). When this happens during the reading of a programmed cell, the node MAT can even arrive at a voltage smaller than the reference voltage VREF, in which case it will provide the comparator with an input signal that does not correspond to that of a programmed cell, but rather to the signal of an erased cell.
An analysis of the circuit system leads one to note that the phenomenon that has just been described can be attenuated by using a transistor T
1
having a large transconductance, i.e., a low resistance while conducting. The charging of the capacitance C
BL
is effected through low-resistance components and is therefore completed at considerable speed. Unfortunately, however, a large transconductance also implies a low reading sensitivity. In fact, in direct-current operation the reading sensitivity, i.e., the ratio between the voltage of node MAT and the current that passes through transistor T
1
, is inversely proportional to th

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