Reading circuit for a memory cell

Details Reading circuit for a memory cell Reading circuit for a memory cell

2001-12-20

2003-03-18

Mai, Son (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185200

Reexamination Certificate

active

06535429

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims priority from prior Italian Patent Application No. MI2000A002763, filed Dec. 20, 2000, the entire disclosure of which is herein incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a reading circuit for a memory cell, particularly for the reading operation of an EEPROM memory cell.
2. Description of Related Art
To perform a reading operation of an EEPROM memory cell it is necessary to apply a suitable voltage to the control gate electrode so as to bias the cell at the desired values.
In applications such as a Smartcard realized in a technology having as a characteristic a channel length of the cells of 0.35 &mgr;m, the usual approach followed is to provide a control gate voltage biasing with a constant current to a virgin EEPROM cell.
This approach shows the advantage that the voltage in this way provided is strictly connected to the technological parameters of the EEPROM cells. Therefore the voltage will be of a suitable value also at the changing of the temperature and process parameters.
To perform the reading operation of the stored charge value in the memory cells a sense amplifier is used.
Another methodology used in EEPROM memories is to bias the diode connected virgin cell at a constant current value, as shown in
FIG. 1
, so as to make full use of its own threshold voltage value as a reference value.
This approach shows, however, the drawback of not reproducing on the virgin cell, taken as reference, the same biasing conditions used during the reading operation of the sense amplifier.
Moreover such biasing technique shows also the drawback that the generator circuit of the control gate voltage, shown in
FIG. 1
, not being provided with an output stage, has a very limited driving capability of the successive stages.
Due to the technological parameters of EEPROM memory cells, the output voltage provided by means of such a methodology is comprised between 2.5V and 3V, values that are higher than the lower supply voltage of the device.
Therefore there is the need to supply the circuit, adapted to provide the control gate voltage, at a higher voltage, called Vboost, with respect to the supply voltage Vcc, that in typical conditions is about Vboost=5.5V.
Moreover the control gate voltage is not provided by a single EEPROM memory cell but by means of a plurality of virgin cells so as to evaluate the possible changes of the process, that influence each memory cell.
This states that since for a single virgin memory cell the current is about ten microampere, thinking that a number “n” of virgin cells are used, the current that theoretically should provide the voltage Vboost is about a few tens of microampere.
In the case in which “n” is eight, the consumption can arrive at about a hundred microamperes.
This causes too high of a static consumption of the control gate voltage source.
SUMMARY OF THE INVENTION
In view of these drawbacks, it is an object of the present invention to overcome the above-mentioned drawbacks and to provide a control gate voltage which is stable with the working parameter changes of the reading system.
Another object of the present invention is to drive successive stages with a suitable control gate voltage.
Yet another object of the present invention is to minimize the current consumption of the Vboost circuit adapted to provide the control gate voltage.
According to a preferred embodiment of the present invention, a reading system of a memory cell includes source means of a reference current, a memory cell having a first, a second, and a third terminal, with the memory cell being biased between the first and second terminal at a predetermined voltage, comparison means for comparing a current flowing in the memory cell with the reference current, and a control gate voltage source applied to the third terminal of the memory cell, with the control gate voltage source including a virgin memory cell having a fourth, fifth, and sixth terminal, the virgin memory cell being biased between the fourth and fifth terminals with a voltage equal to the biasing voltage of the memory cell, and being of identical technological characteristics of the memory cell to be read, and the control gate voltage source producing a control gate voltage at the sixth terminal of the virgin memory cell.
The present invention provides a reading system of an EEPROM memory cell that is strictly connected with the technological parameters of the same EEPROM cells.
Moreover, the present invention reduces the power consumption of the control gate source.
Further, the present invention reduces the dimension of the Vboost source.
Also, the present invention provides the reference voltage in function of one or more EEPROM virgin cells.
Other objects, features, and advantages of the present invention will become apparent from the following detailed description. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the present invention, are given by way of illustration only and various modifications may naturally be performed without deviating from the present invention.


REFERENCES:
patent: 5218570 (1993-06-01), Pascucci et al.
patent: 5267202 (1993-11-01), Dallabora et al.
patent: 5886925 (1999-03-01), Campardo et al.
patent: 6016272 (2000-01-01), Gerna et al.
patent: 6330188 (2001-12-01), Pascucci
patent: 6363015 (2002-03-01), Barcella et al.

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