Reading circuit and method for a nonvolatile memory device

Details Reading circuit and method for a nonvolatile memory device Reading circuit and method for a nonvolatile memory device

2007-06-08

2008-11-11

Nguyen, Dang T (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S210130, C365S189070

Reexamination Certificate

active

07450428

ABSTRACT:
Described herein is a reading circuit for a nonvolatile memory device, wherein the currents flowing through an array memory cell to be read, and a reference memory cell with known contents, are converted into an array voltage and, respectively, into a reference voltage, which are compared to determine the contents of the array memory cell. The method envisages reducing the electrical stress to which the reference memory cell is subjected during reading, by generating and holding a sample of the reference voltage, then deselecting the reference memory cell, and then continuing reading using the sample of the reference voltage.

REFERENCES:
patent: 5351212 (1994-09-01), Hashimoto
patent: 5805500 (1998-09-01), Campardo et al.
patent: 5973959 (1999-10-01), Gerna et al.
patent: 6191989 (2001-02-01), Luk et al.
patent: 6288934 (2001-09-01), Aikawa
patent: 6473340 (2002-10-01), Pasotti et al.
patent: 7116572 (2006-10-01), Sun et al.
European Search Report for EP 04 42 5724 dated Feb. 22, 2005.

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