Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2011-01-04
2011-01-04
Chan, Eddie P (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
Reexamination Certificate
active
07865695
ABSTRACT:
An integrated circuit in communication with a host circuit includes an interconnect bus and a plurality of programmable elements. Each of the programmable elements includes a control interface for receiving a control signal, the control signal causing the memory element to selectively operate in one of a plurality of modes. In a first mode, the memory element communicates stored data to the output port upon receiving the control signal; in a second mode the memory element communicates stored data to the output port upon detecting valid data at the input port; in a third mode the memory element stores a first data value consisting of at least a portion of a single data word received at the input port; and in a fourth mode the memory element stores a second data value consisting of at least a portion of each of two separate input values received at the input port. Each programmable element may write data to and read data from a memory element of any of the other programmable elements.
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Kuo Yea Zong
Yancey Jerry William
Chan Eddie P
Hovey & Williams, LLP
L-3 Communications Integrated Systems L.P.
Petranek Jacob
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