Dynamic magnetic information storage or retrieval – General recording or reproducing – Specifics of biasing or erasing
Reexamination Certificate
2000-11-29
2004-04-13
Hudspeth, David (Department: 2651)
Dynamic magnetic information storage or retrieval
General recording or reproducing
Specifics of biasing or erasing
C360S067000, C360S046000
Reexamination Certificate
active
06721117
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a read/write system for reading information from a magnetic storage medium using a magnetoresistive head and for providing an output signal representative of the information read. In particular, the present invention relates to a read/write system with reduced write-to-read transition recovery time and increased input impedance.
A popular method of magnetic data storage utilizes magnetoresistive (MR) heads to store and recover data on a magnetic data storage medium such as a magnetic disk. An MR head employs an MR element that changes in resistivity with changing magnetic flux from data patterns on an adjacent magnetic disk surface. A bias current having a constant value is passed through the MR element, and the change in resistivity is measured by sensing the change in voltage across the MR head.
Amplifier circuits that sense signals from MR heads commonly include differential inputs and differential outputs. While there are a wide variety of differential amplifier circuit topologies, most include an input stage with a current source, two load resistors, and symmetrical transistors for splitting the current between the load resistors. Usually, the output voltage is taken as the difference in the voltage drops across the load resistors; in this manner, large variations in output voltages may be achieved with extremely small input voltage differentials. Additionally, differential amplifier circuits commonly include an input stage that is capacitively (or ac) coupled to the MR head; in this manner, only changes in input voltage are sensed by the differential amplifier circuit, while dc voltages are ignored.
For all differential amplifier read/write circuits there are associated therewith certain transition recovery time performance characteristics. These characteristics and others determine the usefulness of the read/write circuit in any given application. The write-to-read transition recovery time is the duration of time required for a differential amplifier read/write circuit to switch from write mode to read mode and reach steady state. For differential amplifier read/write circuits that are capacitively coupled to the MR head, the write-to-read transition recovery time is increased due to charging and discharging of the input capacitors. This is caused by the presence of input voltage and input current offset.
Theoretically, if the transistors, as well as the load resistors, in a differential amplifier circuit were perfectly matched and the voltage across the differential inputs was zero, then current would split equally between the transistors and the output voltage would also be zero. Practical circuits, however, exhibit mismatches that result in a nonzero dc output voltage even when the voltage across the inputs is zero. As a result, in order to reduce the output voltage to zero, an input voltage offset must be present between the inputs of the differential amplifier circuit. In addition, in a perfectly matched differential amplifier circuit, the differential inputs carry equal dc currents, otherwise known as input bias currents. Practical circuits, however, exhibit mismatches, particularly in the P of the transistors, that make the input dc currents unequal. The resulting difference is the input current offset.
One well-known modification to the differential amplifier read/write circuit is the addition of a Gm stage, or transconductance amplifier, that is coupled to the transistors of the input stage. The Gm stage provides negative shunt feedback which causes a shunting of the noise resistances of the input transistors and suppresses disturbances caused by the input voltage offset during the transition from write mode to read mode. However, the main disadvantage of this type of circuit is that the negative shunt feedback only compensates the input voltage offset and not the input current offset. Furthermore, because the Gm stage provides negative shunt feedback not only during the transition from write mode to read mode but at all times, the amount of feedback is a tradeoff between write-to-read transition recovery time and input impedance of the differential amplifier read/write circuit. An increase in the transconductance of the Gm stage suppresses disturbances caused by the input voltage offset more quickly and decreases the write-to-read transition recovery time. However, an increase in the transconductance of the Gm stage is equivalent to a decrease in the resistance of the Gm stage. Because the resistance of the Gm stage is directly in parallel to the small-signal model resistances of the input transistors, the input impedance of the differential amplifier circuit decreases, which in turn requires a significant increase in the size of the input capacitors.
Accordingly, there is a need for a read/write system that compensates both input voltage offset and input current offset to reduce write-to-read transition recovery time, while increasing input impedance to reduce the size of the input capacitors.
BRIEF SUMMARY OF THE INVENTION
The present invention is a read/write system for reading information from a magnetic storage medium using a magnetoresistive head and for providing an output signal representative of the information read. A differential pair circuit is ac coupled to first and second input signal nodes and includes first and second transistors, first and second load resistors, and a current generator. An input voltage offset compensation circuit is coupled to the differential pair circuit and includes a switch network and a Gm stage. An input current offset compensation circuit is coupled to the differential pair circuit and includes an integrator circuit and first and second biasing resistors.
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Agere Systems Inc.
Hudspeth David
Kapadia Varsha A
Kinney & Lange , P.A.
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