Read/write memory cell for microcomputer

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365154, G06F 1300

Patent

active

045063222

ABSTRACT:
A system for real-time digital signal processing employs a single-chip microcomputer device having separate on-chip program ROM and data RAM, with separate address and data paths for program and data. The data RAM uses a pseudo-static cell array with refresh. An external program address bus allows off-chip program fetch in an expansion mode, with the opcode returned by an external data bus. A bus interchange module allows transfer between the separate internal program and data busses in special circumstances. The internal busses are 16-bit, while the ALU and accumulator are 32-bit. A multiplier circuit produces a single state 16.times.16 multiply function separate from the ALU, with 32-bit output to the ALU. One input to the ALU passes through a 0-to-15 bit shifter with sign extension.

REFERENCES:
patent: 3962684 (1976-06-01), Caudel et al.
patent: 4184208 (1980-01-01), Tubbs

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