Read-write circuitry for one transistor per bit random access me

Details Read-write circuitry for one transistor per bit random access me Read-write circuitry for one transistor per bit random access me

1975-06-30

1977-01-18

Robinson, Thomas A.

Communications: electrical

Digital comparator systems

340173R, G11C 1140

Patent

active

040042855

ABSTRACT:
A random access memory includes a plurality of one-transistor storage cells. A plurality of sense-write conductors are included, each connected to a plurality of storage cells in a row of storage cells. A plurality of regenerative sense amplifiers are each coupled to two sense-write conductors. A one-transistor dummy storage cell is connected to each sense-write conductor. Read-write circuitry is coupled between a data conductor of the memory chip and a storage node of one of the dummy storage cells of each row of storage cells. The dummy storage cell is selected whenever a storage cell on the opposite side of the regenerative sense amplifier is selected. Charge initially stored in the selected storage cell is redistributed on the opposite sense-write conductor and is subsequently amplified by the sense amplifier, and produced in inverted amplified form at the storage node of the dummy storage cell. Capacitive loading on all of the sense-write conductors of the memory chip during redistribution of charge in the selected storage cell is thereby reduced, thereby increasing the magnitude of the sense-write conductor voltage transitions when a storage cell is selected.

REFERENCES:
patent: 3838295 (1974-09-01), Lindell
patent: 3936810 (1976-02-01), Dunn
Stein et al., "Storage Array and Sense/Refresh Circuit for Single-Transistor Memory Cells," IEEE Journal of Solid-State Circuits, vol. SC-7, No. 5, Oct. 1972, pp. 336-340.

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