Read/write channel

Details Read/write channel Read/write channel

2001-12-18

2003-07-15

Faber, Alan T. (Department: 2651)

Dynamic magnetic information storage or retrieval

Checking record characteristics or modifying recording...

C360S046000, C360S053000, C360S051000, C360S078140, C360S077080, C360S065000

Reexamination Certificate

active

06594094

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to disk drives and, particularly, to an improved read/write channel.
2. Description of the Related Art
In a magnetic recording system, data are encoded and written onto a disk in regions of differing magnetization. To read the data out, they are first detected and then decoded. The writing and reading occurs using a magnetic head, such as inductive heads or magneto-resistive heads.
FIG. 54
illustrates an exemplary read-write channel system according to the prior art. As shown, the system includes an encoder
5402
, read/write head
5404
, disk
5406
, detector
5408
, and decoder
5410
. User data are provided to the encoder
5402
. Once encoded, the input data may be subject to further channel or modulation coding, as well as error correction coding, and are then written onto the disk
5406
by the head
5404
.
To write the channel data onto the disk, the bits are converted into a write current waveform. When the write current waveform takes a positive value, it magnetizes the disk in a first direction; when negative, it magnetizes the disk in a second direction. These states of magnetization are typically described using NRZ or NRZI data. In the NRZ scheme, a one (1) represents one direction of magnetization, and a zero (0) represents another. In the NRZI scheme, a one (1) identifies a transition, and a zero (0) represents no transition.
As noted above, prior to converting the data to the magnetization pattern, it is typically encoded (e.g., using encoder
5402
). The encoding typically minimizes the number of adjacent transitions (to reduce intersymbol interference) and to avoid long strings of zeroes (which can cause problems with channel synchronization and detection.). Coding types include run length limited codes and other known types.
To read the disk
5406
, the head reads an analog signal and provides it to the detector
5408
. A variety of detectors are commonly used. These include peak detectors or sampled data detection techniques. The detector
5408
recovers the data and provides it to the decoder
5410
, which decodes the channel data.
In sampled data detection systems, the readback signal is filtered and sampled at a channel rate of 1/T, where T is the duration of a channel symbol. One such technique is referred to as “partial response with maximum likelihood” (PRML). In PRML systems, the output of the noisy partial response channel is sampled at the channel rate and detected using a maximum likelihood Viterbi detector.
The partial response channel has a transfer function of the form (1−D)(1+D) or 1−D
2
, where D represents a unit time delay operator with unit-time T. Thus, the noiseless output of the partial response channel is equal to the input signal minus a version of the input delayed in time by period 2T.
To further increase recording density and decrease the need for equalization, higher order PRML systems have been developed. The extended partial response with maximum likelihood (EPRML) channel has a transfer function of the form (1−D)(1+D)
2
or (1+D−D
2
−D
3
). Thus, the noiseless output of the extended partial response channel is equal to the input signal minus a version of the input signal delayed in time by 2T, minus a version of the input signal delayed in time by 3T and plus a version of the input signal delayed in time by T. Similarly, the E
2
PRML channel has a transfer function of the form (1−D)(1+D)
3
.
As noted above, Viterbi decoders are typically employed in sampled amplitude channels. Viterbi decoders are specific implementation of the Viterbi algorithm. A Viterbi detector unit is based on periodic examination of metrics associated with alternate sequences of recorded bits, wherein each sequence is typically labeled as a “path” and the associated metric is designated a “path metric.” The most probable correct path is then determined by choosing a minimum path metric based on an iterative process involving successive comparison of associated path metrics.
In particular, two paths within a constrained, predetermined path length are examined. Since the recorded bit only depends on the constraint length corresponding to a finite number of neighbor bits, it becomes possible to abandon the path associated with the larger of the two path metrics corresponding to each path pair. Consequently, the number of possible paths can be restricted to a finite value by abandoning all but one of the total number of paths each time a new bit is added and examined during the data detection procedure. This process of path abandonment in order to compute the best path to each node of the trellis is executed by a sequence of operations commonly referred to as add-compare-select or ACS.
SUMMARY OF THE INVENTION
According to one embodiment of the present, an improved sampled amplitude read/write channel is provided. The system is an integrated Generalized Partial Response Maximum Likelihood (GPRML) read channel incorporating Read, Write, and Servo modes of operation. One implementation includes a 32/34 rate parity code and matched Viterbi detector, a 32 state Viterbi detector optimal parity processor, robust frame synchronization, self-adaptive equalization, thermal asperity detection and compensation, adaptive magneto-resistive asymmetry compensation, low latency interpolated timing recovery and programmable write precompensation.


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Altekar et al., “A 700Mb/s BiCMOS Read Channel Integrated Circuit,”2001 IEEE International Solid-State Circuits Conference, XP-002177065, 3 pgs.
Bloodworth et al., “A 450-Mb/s Analog Front End for PRML Read Channels,”IEEE Journal of Solid-State Circuits, XP-000931893, 1999, 34(11):1661-1675.
Chern et al., “SA 19.4: An EPRML Digital Read/Write Channel IC,”IEEE International Solid-State Circuits Conference, XP-002177066, 1997, 8 pgs.
Chern et al., “SA 19.4: An EPRML Digital Read/Write Channel IC,”IEEE International Solid-State Circuits Conference, XP-000753116, 1997, pp. 320-321, 479.
Fields et al., “SA 19.1: A 200Mb/s CMOS EPRML Channel with Integrated Servo Demodulator for Magnetic Hard Disks,”IEEE International Solid-State Circuits Conference, XP-000999335, 1997, pp. 314-315, 477.

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