Static information storage and retrieval – Floating gate – Data security
Reexamination Certificate
2001-06-27
2002-02-19
Phan, Trong (Department: 2818)
Static information storage and retrieval
Floating gate
Data security
C365S185090
Reexamination Certificate
active
06349057
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a read protection circuit for nonvolatile memory, and more particularly to a read protection circuit for writing read protection data including information as to whether read protection is provided or not into nonvolatile memory capable of electrically writing and reading and reading out this read protection data and performing read protection control of the nonvolatile memory.
In nonvolatile memory (EEPROM) capable of electrically writing, reading and erasing, there is no need for battery backup and also data can be rewritten electrically, so that the nonvolatile memory has widely been used in applications such as program storage memory of a microcomputer or an IC card.
In a microcomputer with built-in EEPROM, there is a need to ensure security so that a third party cannot have access to user's program data stored in the EEPROM. On the other hand, since a CPU operates based on a command in which program data read from the EEPROM is decoded, the CPU needs to perform readout from the EEPROM naturally.
Thus, in a conventional microcomputer with built-in EEPROM, information as to whether read protection (read inhibition) of the EEPROM is provided or not was written into read protection memory and based on this information, read protection control was performed.
A read protection circuit of a conventional example will be described below with reference to the accompanying drawing.
FIG. 4
is a schematic diagram showing a configuration of EEPROM and a peripheral circuit. A memory mat
51
including plural EEPROM memories capable of electrically writing, reading and erasing is constructed of a main memory area
52
, a redundancy memory area
53
for replacing a defective memory area occurring in the main memory area, and an inforow memory area
54
for storing various manufacturing information.
Also, numeral
55
is read protection memory for storing read protection data including information as to whether read protection is provided or not, and is provided as dedicated memory in an area physically distant from the memory mat
51
described above.
Then, control is performed whether external output of data from the main memory area
52
is permitted or inhibited (read protection) on the basis of the read protection data read from the read protection memory
55
under predetermined conditions.
However, the read protection memory
55
is dedicatedly provided in an area physically distant from the memory mat
51
on a chip, so that there is the need to dedicatedly provide an analog control circuit such as an analog bias circuit used in data writing and there is a problem that a circuit scale becomes large.
Also, the need to change the number of read protections according to specifications of a type of machine arises. For example, there are an external ROM mode, a flash mode, etc. as a kind of modes for providing read protection. Thus, when a size of the read protection memory
55
is changed, there is a problem that a change in a layout of a chip is difficult since the read protection memory
55
is provided in an area physically distant from the memory mat
51
.
SUMMARY OF THE INVENTION
Therefore, an object of the invention is to eliminate the need to dedicatedly provide a control circuit such as an analog bias circuit by forming read protection memory within the same memory mat as a main memory area to reduce a circuit scale or facilitate expansion and reduction of the read protection memory to reduce a chip size.
A redundancy memory circuit of the invention comprises a main memory area including of plural nonvolatile memories capable of electrically writing and reading, a read protection memory area provided within the same memory mat as the main memory area, means for writing read protection data including information as to whether read protection is provided or not into the read protection memory area, means for reading the read protection data stored in the read protection memory area according to a trigger signal, register means for temporarily storing the read protection data read from the read protection memory area, and gate means for setting a data output read from the main memory area in a read protection state according to output data of the register means.
In accordance with such means, the read protection memory area is formed within the same memory mat as the main memory area, so that the need to dedicatedly provide a dedicated EEPROM cell for storing read protection data and an analog control circuit for writing the read protection data into this EEPROM cell is eliminated and a chip size can be reduced.
Also, a size of the read protection memory area can be changed easily, so that memory design according to specifications of a type of machine can be performed in a short time while the chip size can be reduced.
REFERENCES:
patent: 5812446 (1998-09-01), Tailliet
patent: 6034889 (2000-03-01), Mani et al.
patent: 6088262 (2000-07-01), Nasu
patent: 6104634 (2000-08-01), Rochard
patent: 6108235 (2000-08-01), Honma
patent: 6266271 (2001-06-01), Kawamura
Fish & Richardson P.C.
Phan Trong
Sanyo Electric Co,. Ltd.
LandOfFree
Read protection circuit of nonvolatile memory does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Read protection circuit of nonvolatile memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Read protection circuit of nonvolatile memory will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2953182