Read-out amplifier circuit for a dynamic MOS memory

Details Read-out amplifier circuit for a dynamic MOS memory Read-out amplifier circuit for a dynamic MOS memory

1977-05-19

1978-10-10

Anagnos, Larry N.

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307246, 307279, 307DIG3, 365204, 365205, H03K 520, G11C 706, H03K 3353, H03K 3286

Patent

active

041198700

ABSTRACT:
A read-out amplifier circuit for a dynamic MOS memory has two arms each of which includes a switching transistor and a load transistor connected in series, the arms being connected in parallel with a feedback connection between the junction of a switching transistor and a load transistor and the control electrode of the switching transistor of the other arm. The junctions of the switching transistors and load transistors are connected to respective sub-portions of a bit line and are also connected by way of a balance transistor. The source electrodes of the switching transistors are connected to a node which is charged prior to the beginning of a reading cycle and, for evaluating a read-out signal, is discharged in a controlled manner such that the switching transistor whose drain electrode is subjected to the voltage change which gives rise to the read-out signal is rendered conductive. Following the charging of the node, the load transistors are disconnected and the balance transistor is conductive so that the voltage existing across the node influences the junction points. Then the balance transistor is disconnected and during a subsequent evaluation of a read-out signal, the controlled discharge of the node causes the other switching transistor to temporarily pass into the conductive state.

REFERENCES:
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patent: 3978459 (1976-08-01), Koo
patent: 3993917 (1976-11-01), Kalter
patent: 4004284 (1977-01-01), Heeren
patent: 4025907 (1977-05-01), Karp et al.
patent: 4028557 (1977-06-01), Wilson
patent: 4061999 (1977-12-01), Proebsting et al.
Bishop, "High-Sensitivity, High-Speed FET Sense Latch," IBM Tech. Discl. Bull.; vol. 18, No. 4, pp. 1021-1022; 9/1975.
Stein et al., IEEE Journal of Solid-State Circuits; vol. SC-7, No. 5, pp. 336-340; 10/1972.

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