Read only semiconductor memory having multiple bit cells

Details Read only semiconductor memory having multiple bit cells Read only semiconductor memory having multiple bit cells

1987-04-22

1989-07-11

Moffitt, James W.

Boots, shoes, and leggings

365168, 365184, 357 2312, G11C 1700

Patent

active

048478083

ABSTRACT:
For precise read-out operation at an improved speed, there is disclosed a semiconductor memory device fabricated on a semiconductor substrate of a first conductivity type and including a plurality of memory cells, each memory cell comprising (a) an insulating film covering a surface portion of the semiconductor substrate, (b) a gate electrode formed on the insulating film and located over a channel forming region in the surface portion of the semiconductor substrate, a channel being produced in the channel forming region when the memory cell is selected, (c) a first impurity region having a second conductivity type opposite to the first conductivity type and formed in the surface portion of the semiconductor substrate, the first impurity region being contiguous to the channel forming region or spaced apart from the channel forming region depending upon a bit of information stored therein, and (d) a second impurity region of the second conductivity type formed in the surface portion of the semiconductor substrate, the second impurity region being contiguous to the channel forming region or spaced apart from the channel forming region depending upon a bit of information stored therein.

REFERENCES:
patent: 4272830 (1981-06-01), Moench
patent: 4503518 (1985-03-01), Iwahashi
patent: 4596453 (1985-10-01), Noufer
Bayliss et al, "The Interface Processor for the 32b Computer", IEEE International Solid State Circuits Conference, Digest of Technical Papers, Feb. 1981, pp. 116-117.

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