Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2002-06-14
2004-09-28
Phung, Anh (Department: 2824)
Static information storage and retrieval
Interconnection arrangements
C365S185050
Reexamination Certificate
active
06798680
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the forming in integrated form of memories. More specifically, the present invention relates to the integration of read-only memories (ROMs).
2. Description of the Related Art
Such memories are intended for the storing of data or functions intended to be always available and not reprogrammable.
Upon design of an integrated circuit including such a ROM, at least one prototype memory circuit, especially intended to test whether the data provided to be stored in the memory enable fulfilling desired functions, is formed.
To reduce the number of formed prototypes, it has been provided to form the prototype memory in the form of a programmable array. It is thus possible to modify the number and the arrangement of programmed or unprogrammed cells of the memory array in successive checking operations.
To form the programmable prototype memory, electrically-programmable cells erasable by being exposed to ultraviolet rays may be used.
FIG. 1A
illustrates the equivalent electric diagram of an embodiment of such a cell
1
. Cell
1
includes, between a selection line SL and a bit line BL, the series connection of a memory element and of a selection element. The memory element is a P-channel MOS transistor
2
, gate
3
of which is unconnected. The selection element is a MOS transistor
4
. As a non-limiting example, it will be considered in the following description that selection transistor
4
is an N-channel transistor. However, it could also be a P-channel transistor. Gate
5
of transistor
4
is connected to a read line RL.
FIG. 1B
illustrates an embodiment in integrated form of the cell of FIG.
1
A.
Memory transistor
2
is formed in a first active area
6
of a silicon substrate. A channel area of transistor
2
, defined by unconnected isolated gate
3
, separates, in active area
6
, source
7
and drain
8
of transistor
2
. Selection line SL is in contact with source
7
. Drain
8
is integral with one end of a conductive connection
9
. The other end of conductive connection
9
is in contact with source
10
of selection transistor
4
. Selection transistor
4
is formed in a second active area
11
of the same substrate as first active area
6
. Source
10
of transistor
4
is separated from drain
12
by a channel area defined by isolated gate
5
, formed on area
11
. Drain
12
of selection transistor
4
is in contact with bit line BL.
In the forming of a complete array, selection and read lines SL and RL are common to the cells of a same row, while bit line BL is common to the cells of a same column.
The operation of a programmable array formed of cells identical to cell
1
of
FIG. 1
is the following. When a datum is desired to be programmed in a cell, this cell is selected via appropriate signals on read line RL to turn selection transistor
4
on. In the considered case of an N-channel selection transistor
4
, read line RL, that is, gate
5
of transistor
4
, is brought to a high biasing level VDD. Line BL is grounded. Selection line SL (source
7
of transistor
2
) is brought to a programming level VPP raised with respect to high level VDD. The insulator of gate
3
of memory transistor
2
is chosen to enable in these conditions the passing of electrons on gate
3
(programming by hot electrons).
The reading of a datum stored in a programmable cell
1
is performed as follows. Selection line SL is brought to high level VDD. Gate
5
of transistor
1
is biased to level VDD to turn on selection transistor
4
. Then, if memory transistor
2
has been previously programmed, it is at least partially conductive due to the charges accumulated on its unconnected gate
3
. The voltage level copied by selection transistor
4
on bit line BL then is relatively close to high level VDD. However, if memory transistor
2
has undergone no programming, it is totally non-conductive (off) and line BL is brought to a relatively low level with respect to high level VDD.
To determine the data to be contained in the programmable array, the following step succession is repeated:
programming such a memory array;
testing the circuit operation; and
erasing with ultraviolet rays the array data.
These steps are repeated until the functional test is satisfactory. Once the number of programmed and unprogrammed (blank) cells and their configuration specific to the desired operation have been determined, a definitive integrated circuit including a read-only memory is manufactured.
Thus, the conventional industrial process of manufacturing of an integrated circuit containing immovably stored data includes the steps of manufacturing a prototype circuit containing a programmable memory, then a definitive circuit containing a definitive ROM, the definitive ROM containing for example a simple transistor at the level of each memory point and being clearly distinct from the programmable memory. This requires, for each circuit, manufacturing two sets of masks very different from each other.
BRIEF SUMMARY OF THE INVENTION
An embodiment of the present invention provides for a method and device for simplifying this manufacturing process.
The applicant has noticed that the general manufacturing cost of prior art designs (prototype memory plus definitive memory) may be higher than the gain resulting from the inserting of an optimized ROM in the definitive circuit.
Thus, an embodiment of the present invention provides a read-only memory which is slightly different from a programmable memory.
Another embodiment of the present invention provides a ROM which can be easily formed in a memory array also including a programmable sector.
Another embodiment of the present invention provides a method for converting a programmable memory into a ROM which is compatible with the above embodiments.
An embodiment of the present invention provides a read-only memory formed of cells, each of which includes, between a selection line and a bit line, the series connection of a memory element and of a selection MOS transistor with a gate connected to a read control line. The memory elements of blank cells are P-channel MOS transistors and the memory elements of programmed cells are uniformly N-type doped semiconductor regions.
According to an embodiment of the present invention, the gates of the memory transistors of the blank cells are unconnected.
According to an embodiment of the present invention, the selection transistor of at least one blank cell is an N-channel transistor and the gates of the memory and selection transistors of said at least one blank cell are interconnected by a conductive connection.
According to an embodiment of the present invention, the read-only memory is formed in the same integrated circuit chip as a programmable memory formed of cells including, between a selection line and a bit line, the series connection of a P-channel MOS transistor, the gate of which is unconnected, and of a MOS transistor, the gate of which is connected to a read control line, the lines of selection of the read-only and programmable memories being connectable to a selection power supply and the lines of selection of the sole programmable memory being selectively connectable to a write power supply distinct from said selection power supply.
An embodiment of the present invention also provides a method for forming, in a single-crystal semiconductor substrate, a read-only memory, including the steps of defining first and second active areas of same dimension; forming isolated lines above the second areas and some of the first areas; implanting the exposed portions of said first and second active areas; depositing an insulator over the entire structure; opening said insulator to partially expose each of the first and second areas, in the vicinity of each of its ends; and forming selection lines in contact with the first active areas, conductive connections to match each first active area with a second active area, and bit lines in contact with said second active areas.
The foregoing embodiments of the present invention will be disc
Iannucci Robert
Jorgenson Lisa K.
Nguyen Tuan T.
Phung Anh
STMicroelectronics S.A.
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