Read only memory with write operation using mask

Details Read only memory with write operation using mask Read only memory with write operation using mask

1990-09-18

1991-10-22

Fears, Terrell W.

Static information storage and retrieval

Read only systems

Semiconductive

365 51, G11C 1300

Patent

active

050601903

ABSTRACT:
An FET ROM and a manufacturing process in which ROM's can be stockpiled after the gates have been formed and the source and drain implants have been made but before the write operation has been performed. At this stage, the unwritten ROM has an array of enhancement mode FET's connected in a logical NAND configuration with an overlying layer of insulation. For a write operation, the insulation is removed to expose the drain and source regions of the FET's, a conductive layer is formed over the array, and the layer is selectively etched to leave a short circuit element between the drain and source of those FET's that are to store a binary 0 and to leave switchable the FET's that are to store a 1.

REFERENCES:
patent: 4565712 (1986-01-01), Noguchi

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