Read-only memory with complementary data lines

Static information storage and retrieval – Read only systems – Semiconductive

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Details

365154, 36518905, 36518906, 365190, 365203, 365205, 365208, G11C 1712

Patent

active

053093895

ABSTRACT:
A plurality of single transistor memory cells arrayed in columns with the memory cells within a column connected to one or the other of precharged first and second output lines. An input line connected to the gate of the single transistor causes the first output line to be pulled to a first voltage when the cell is programmed a "true" and to be pulled to a second voltage when the cell is programmed a "complement". A pair of cross-coupled transistors connected between the first and second output lines of a column cause the second output line to be maintained at the precharged voltage when programmed a "true" and causes the first output line to be maintained at a precharged voltage when programmed a "complement".

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