Read only memory using series connected depletion transistors as

Static information storage and retrieval – Read only systems – Semiconductive

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365 94, 357 45, G11C 502, G11C 506, G11C 1700

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active

044942184

ABSTRACT:
The memory circuit is formed by depositing spaced, parallel polysilicon strips on an insulating layer on the surface of the substrate. Spaced, parallel, elongated regions, which extend in a direction orthogonal to the strips, are formed in the substrate. Each elongated region comprises diffused segments (forming sources and drains) separated by non-diffused areas, masked by the strips, (forming channels). Spaced regions, extending parallel to the strips, are diffused to interconnect adjacent ones of the elongated regions, at intervals therealong. The strips are also subjected to the diffusion to produce conductivity appropriate for functioning as gates and gate interconnections. The elongated regions each form series connected enhancement mode devices of relatively low thresholds. Alternate elongated regions are subjected to a first implant to convert same into series connected depletion mode devices. The channels of certain of the enhancement devices, selected in accordance with the desired memory program, are subjected to a second implant to increase the threshold thereof. By applying a voltage, between the lower and higher thresholds, to a strip and creating a potential difference between adjacent alternate elongated regions, the enhancement device at the intersection of the elongated region between the adjacent alternate elongated regions and the strip is read to ascertain if same has been rendered conductive, thereby producing a memory output.

REFERENCES:
patent: 4059826 (1977-11-01), Rogers
patent: 4084105 (1978-04-11), Teranishi et al.
patent: 4207585 (1980-06-01), Rao
patent: 4271421 (1981-06-01), McElroy
patent: 4342100 (1982-07-01), Kuo
patent: 4350992 (1982-09-01), Tubbs
patent: 4384345 (1983-05-01), Mikome

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