Read only memory (ROM) having high density memory array with on

Details Read only memory (ROM) having high density memory array with on Read only memory (ROM) having high density memory array with on

1981-09-04

1983-12-06

Hecker, Stuart N.

Static information storage and retrieval

Interconnection arrangements

Transistors or diodes

365105, G11C 506, G11C 1706

Patent

active

044197411

ABSTRACT:
The ROM utilizes a diode x-y memory array which can be comprised of a number of suitable materials which form rectifying junctions. The diodes are formed vertically in order to provide a very high density array. On pitch decoder circuitry which is capable of matching the high density of the memory cells in the x-y memory array is also described, as is a unique apparatus for joining adjacent ends of conductive lines which are spaced very close together without increasing their pitch.

REFERENCES:
patent: 3671948 (1972-06-01), Cassen et al.
patent: 3774170 (1973-11-01), Koch
patent: 3909808 (1975-09-01), Cochran et al.
patent: 3965568 (1976-06-01), Gooch
patent: 4069427 (1978-01-01), Masuda
patent: 4088546 (1978-05-01), Wu et al.
patent: 4124900 (1978-11-01), Smith et al.
patent: 4151020 (1979-04-01), McElroy
patent: 4163242 (1979-06-01), Stein
P. C. Arnett et al., Nonvolatile Diode Cross-Point Memory Array, IBM Tech. Discl. Bul., vol. 17, No. 2, Jul. 1974, p. 365.
H. Kawagoe et al., Minimum Size ROM Structure Compatible with Silicon-Gate E/D MOS LSI, IEEE Journal of Solid-State Circuits, vol. SC-11, No. 3, Jun. 1976, pp. 360-364.
L. Boysel, Memory on a Chip: A Step Toward Large-Scale Integration, Electronics, Feb. 6, 1967, pp. 93-98.
K. Clark, Jr., et al., Electron-Beam Stitching Technique for Use in the Fabrication of Integrated Circuit Devices, IBM Tech. Discl. Bul., vol. 23, No. 7A, Dec. 1980, pp. 2774-2775.
S. --Y. Wu, A Hybrid Mass-Interconnection Method by Electroplating, IEEE Transactions on Electron Devices, vol. ED-25, No. 10, Oct. 1978, pp. 1201-1203.

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