Static information storage and retrieval – Read only systems
Reexamination Certificate
2003-06-04
2004-11-30
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Read only systems
26
Reexamination Certificate
active
06826070
ABSTRACT:
BACKGROUND OF INVENTION
This U.S. nonprovisional patent application claims priority under 35 U.S.C. §119 of Korean Patent Application 2002-45692 filed on Aug. 1, 2002, the entire contents of which are hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a read only memory(ROM) cell capable of storing at least two bits of data, a program method of the ROM cell, a layout method of the ROM cell, and a ROM device comprising the ROM cell.
2. Description of Related Art
A conventional read only memory (ROM) device includes a plurality of ROM cells, each having an NMOS transistor with a source connected to a ground voltage, a drain connected or not connected to a bit line and a gate connected to a word line.
Data “0” of the conventional ROM cell is programmed by connecting the drain of the NMOS transistor to the bit line and data “1” of the conventional ROM cell is programmed by not connecting the drain of the NMOS transistor to the bit line. That is, data “0” is programmed in the ROM cell by forming a discharging path through the NMOS transistor and data “1” is programmed in the ROM cell by not forming the discharging path through the NMOS transistor. Generally, such programming is accomplished using a front-end layer forming the NMOS transistor of the ROM cell to more highly integrate the ROM cells in a ROM device.
FIG. 1
illustrates a block diagram of a conventional ROM device. Referring to
FIG. 1
, the ROM device includes a memory cell array
10
, a row decoder
12
, a pre-charge circuit
14
, a data transmission gate
16
, a column decoder
18
, and a data output circuit
20
. The ROM device also includes a plurality of bit lines BL
1
-BLj and a plurality of word lines WL
1
-WLi. The operation of each block in
FIG. 1
is described below.
The memory cell array
10
includes a plurality of memory cells, each cell having a gate connected to a corresponding word line of word lines WL
1
-WLi, a source connected to a ground voltage line and a drain connected or not connected to a corresponding one of bit lines BL
1
-BLj. The ROM cell having a drain connected to the bit line is programmed with data “0”. The ROM cell having a drain not connected to the bit line is programmed with data “1”. The row decoder
12
decodes a row address RA and selects one of the word lines WL
1
-WLi. The pre-charge circuit
14
pre-charges the bit lines BL
1
-BLj to a logic “high” level during a pre-charge operation. The data transmission gate
16
transfers data from the bit lines BL
1
-BLj to the data output circuit
20
, in response to respective column selection signals Y
1
-Yj. The column decoder
18
decodes a column address CA and selects a column selection signal of the column selection signals Y
1
-Yj. The data output circuit
20
receives the data from the data transmission gate
16
and outputs an output data Dout. The overall operation of the conventional ROM device is described below.
During a read operation, the pre-charge circuit
14
pre-charges the bit lines BL
1
-BLj to a logic “high” level.
A word line WL
1
is selected and NMOS transistors N connected to the word line WL
1
are turned on. If bit lines BL
1
and BLj are connected to the ground voltage line, current flows from the bit lines BL
1
and BLj to the ground. As a result, the bit lines BL
1
and BLj have a logic “low” level. If a bit line BL
2
is not connected to the ground voltage line, charges are not drawn to the ground voltage line, so that the bit line BL
2
maintains a logic “high” level.
If a column selection signal Y
1
is generated, a logic “low” level of the bit line BL
1
is output from the data transmission gate
16
.
As described above, the conventional ROM device is disadvantageous in that it stores only one bit of data into a cell.
Further, the conventional ROM device is disadvantageous in that there is a difference in parasitic capacitances between bit lines, which negatively affects circuit operation. Accordingly, an additional circuit for compensating for parasitic capacitance difference is necessary. The additional circuit may cause problems, such as layout area increase, power consumption increase and slow operating speed.
Minimum parasitic capacitance and maximum parasitic capacitance of the bit line are obtained as follow. If all the NMOS transistors connected to the same bit line are programmed to store data “0”, the parasitic capacitance of the bit line is obtained by following equation:
Parasitic Capacitance=
i
×drain capacitance of an NMOS transistor+line capacitance of a bit line, (1)
where i denotes the number of NMOS transistors connected to a bit line.
In the case that all the NMOS transistors connected to the same bit line are programmed to store data “1”, the parasitic capacitance of the bit line is obtained by following equation:
Parasitic Capacitance=0×drain capacitance of an NMOS transistor+line capacitance of a bit line (2)
As a result, a difference between the maximum and minimum parasitic capacitances of bit lines equals i×drain capacitance of an NMOS transistor.
FIG. 2
illustrates another conventional ROM device. The ROM device of
FIG. 2
is similar to the ROM device of
FIG. 1
except that adjacent NMOS transistors N have a common source, connected to a ground voltage line. The ROM device of
FIG. 2
employs only one ground voltage line unlike the ROM device of
FIG. 1
in which two ground voltage lines are employed. Accordingly, a layout area of the ROM device of
FIG. 2
may be smaller than that of the ROM device shown in FIG.
1
.
However, even though the ROM device of
FIG. 2
has an advantage in that the layout area is smaller, the ROM device of
FIG. 2
has the same other disadvantages as the ROM device of FIG.
1
.
Further, in the case of programming the ROM cell using a back-end layer, an active area is designed to dominate an additional area. Accordingly, a layout area of the ROM cell programmed using the back-end layer is larger than that of a ROM cell programmed using a front-end layer. Therefore, the ROM cell is generally programmed by using the front-end layer to increase integration density.
When programming the ROM cell using a front-end layer, since programming may be performed before data to be stored in the ROM cell is determined or confirmed, the programmed ROM device should be re-programmed in several times due to a customer's demand. Accordingly, back-end layer programming is more convenient than front-end layer programming.
SUMMARY OF THE INVENTION
In exemplary embodiments, the present invention provides a read only memory (ROM) cell capable of storing at least two bits of data, in which parasitic capacitances of respective bit lines are substantially the same.
In exemplary embodiments, the present invention also includes a method for programming a ROM cell and a layout method of a ROM cell. The layout method may reduce the layout size of the ROM cell even though the ROM cell is programmed by using a back-end layer.
In exemplary embodiments, the present invention further provides a ROM device comprising a ROM cell.
In an exemplary embodiment, the present invention provides a read only memory (ROM) cell having a gate connected to a word line, a drain (or a source) connected to a bit line, and a source (or a drain) connected to a ground voltage line, a first selection signal line, a second selection signal line, or not connected to any signal lines. The word line, the bit line and the first and second selection signal lines may be at ground voltage level before a read operation starts, and the word line, the bit line and one of the first and second selection signal lines transit to a power supply voltage level during the read operation. In an exemplary embodiment, the word line may be selected by a row address, and the bit line, the first selection signal line and the second selection signal line may be selected by a column address.
In another exemplary embodiment, the present invention provides
Byun Hyoung-Yun
Choo Yong-jae
Sung Nak-Woo
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