Read only memory integrated semiconductor device

Details Read only memory integrated semiconductor device Read only memory integrated semiconductor device

2000-06-09

2001-10-16

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Read only systems

Semiconductive

C365S103000, C365S072000, C365S063000, C365S051000, C365S168000, C365S189080

Reexamination Certificate

active

06304480

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to digital storage devices, and, more particularly, to read only memories (ROMs).
BACKGROUND OF THE INVENTION
Conventional read only memories include a network of elementary memory cells (or memory points) arranged in lines (or rows) and columns. All the memory cells in a line are activated by a first metallization or connection (i.e., a word line), while all the cells in a column can be read based on the voltage across the terminals of a column's connection or bit lines. That is, the activation of a word line and the measurement of the voltage across the terminals of a bit line make it possible to read the content of the memory cell situated at the intersection of the word line and the bit line. The value of the information stored depends on the level (high or low) of the voltage on the bit line. Accordingly, with a conventional read only memory cell it is only possible to code or store a digital word of one bit (which can be zero or one).
SUMMARY OF THE INVENTION
One object of the invention is to provide a read only memory integrated device offering a greater storage density by allowing more than one bit per memory cell.
Another object of the invention is to provide increased reading speed for each cell.
Yet another object of the invention is to provide a read only memory integrated circuit device with cells that can store words of several bits (for example, four bits) and has a reduced size relative to the read only memory devices of the prior art previously required to store several bits.
These and other objects, features, and advantages in accordance with the present invention are provided by a read only memory integrated semiconductor device including at least one memory cell comprising a storage transistor formed within a semiconductor substrate and whose source is grounded, a first connection line (word line) connected to the gate of the transistor, and at least two auxiliary connection lines (bit lines), only one of which may be linked to the drain of the transistor at a time.
In other words, rather than a single bit line, at least two bit lines are associated with each memory cell. Also, to avoid a short-circuit between the bit lines, only a single bit line may be connected to the drain of the transistor at a time. This makes it possible to store more than two values per memory cell; for example, four values for three bit lines forming a digital word of two bits may be stored. The choice of the bit line to be linked to the drain of the transistor depends on the value of the binary information to be stored or written into the memory cell during its fabrication. Of course, it is also possible not to link any of the bit lines to the drain of the transistor, thus making it possible to store a particular value of the digital word contained in the memory cell.
The auxiliary connection lines (bit lines) can be parallel and situated one above another respectively at different metallization levels above the semiconductor substrate. Multi-level memory cells are thus obtained.
Apart from increasing the storage density, the present invention makes it possible to make storage transistors of greater size, thus allowing faster reading of the content of the selected memory cell. Furthermore, the auxiliary connection lines may be parallel and situated alongside one another on the same metallization level.


REFERENCES:
patent: 5289406 (1994-02-01), Uramoto et al.
patent: 5771208 (1998-06-01), Iwase et al.
patent: 41 27 549 (1992-03-01), None
patent: 04276659 (1992-10-01), None
patent: 08064695 (1996-03-01), None

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