Read only memory including an isolation network connected betwee

Details Read only memory including an isolation network connected betwee Read only memory including an isolation network connected betwee

1984-11-23

1987-03-17

Moffitt, James W.

Static information storage and retrieval

Read only systems

Semiconductive

365189, 307530, G11C 1700

Patent

active

046513027

ABSTRACT:
A read only memory utilizing a two-level cascoded current steering approach feeding a two-level common base isolation and sense amplifier network. The isolation network allows formation of a multi-way collector dot without deleterious effect upon the high speed current sensing operation. Single transistor cells with a common subcollector bed and common base rails as word lines make up the highly dense high speed array. The current source is provided by a current mirror circuit. The common-base, low impedance sense amplifier converts the sense current signal into a voltage swing which is then fed to the off-chip driver circuit via an emitter-follower pre-driver stage.

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Montegari et al, "Current Biased Array Sense Circuit", IBM Tech. Discl. Bull., vol. 24, No. 1B, Jun. 1981, pp. 493-494.
Bellis et al, "High Speed Sense Amplifier and Dual Phase Output Circuit", IBM Technical Disclosure Bulletin, vol. 26, No. 7B, Dec. 1983, pp. 3651-3652.
Denis et al, "Quasi-Insensitive Memory Sense Amplifier to Dotting and Wiring Capacitance", IBM Tech. Disc. Bull., vol. 24, No. 6, Nov. 1981, pp. 3060-3061.
"Monolithic Read-Only Storage Circuit", by J. L. Cross, IBM Technical Disclosure Bulletin, vol. 13, No. 9, Feb. 1971, pp. 2770-2771.

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