Static information storage and retrieval – Read only systems – Semiconductive
Reexamination Certificate
2000-09-14
2002-06-11
Mai, Son (Department: 2818)
Static information storage and retrieval
Read only systems
Semiconductive
C365S208000, C365S210130
Reexamination Certificate
active
06404666
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a read only memory (hereinafter, referred to as “ROM”), and more particularly to a read error preventive technology in a large scale ROM.
Referring to
FIG. 2
, there is shown a schematic constitutional diagram of a conventional ROM.
The conventional ROM has column lines CLi (i=1 to m) and word lines WLj (j=1 to n) arranged intersecting the column lines. At intersections between the column lines CLi and the word lines WLj, memory cells
1
i,j
formed by N-channel insulated gate transistors (hereinafter, an insulated gate transistor is referred to as “MOS” and an N-channel MOS is as “NMOS”) are selectively arranged and drains of the memory cells
1
i,j
are connected to the column lines CLi and gates of the memory cells are connected to the word lines WLj. Sources of the memory cells
1
i,j
are connected to ground potential GND via a conductive line.
Respective column lines CLi are connected in common to a bit line BL via P-channel MOS (hereinafter, referred to as “PMOS”) transistors
2
i
. Selection signals SLi are given to gates of the respective PMOS transistors
2
i
for selecting one of the PMOS transistors
2
i
so as to be set on. Furthermore, respective column lines CLi are connected to a power supply potential VCC via PMOS transistors
3
i
controlled in common by a pre-charge signal PR. The bit line BL is connected to the power supply potential VCC via a PMOS transistor
4
which is constantly on.
The ROM has a reference column line CLr arranged intersecting word lines WLj. At each intersection between the reference column line CLr and each word line WLj, each reference memory cell
5
j formed by an NMOS transistor is arranged and a drain of the reference memory cell
5
j is connected to the reference column line CLr and its gate is connected to the word line WLj. A source of each reference memory cell
5
j is connected to ground potential GND. The column line CLr is connected to a reference bit line BLr via a PMOS transistor
6
controlled by a selection signal SLr and connected to the power supply potential VCC via a PMOS transistor
7
controlled by the pre-charge signal PR. The reference bit line BLr is connected to the power supply VCC via a PMOS transistor
8
which is constantly on.
The bit line BL and the reference bit line BLr are connected to a sense amplifier
9
. The sense amplifier
9
amplifies an electric potential difference between the bit line BL and the reference bit line BLr and outputs a status of a selected memory cell
1
i,j
as an output signal Q.
In the conventional ROM, each memory cell
1
i,j
is set to a logical value “0” or “1” at manufacturing. For example, in a contact ROM, a conductive line between a source of a memory cell
1
i,j
and the ground potential GND is connected in a contact layer and the memory cell is set to “1,” while the sources are disconnected from the ground potential GND without a formation of the contact layer and the memory cell is set to “0.” Therefore, if the selected memory cell
1
i,j
is set to “1,” the memory cell
1
i,j
is set on, by which current flows. If it is set to “0,” the current does not flow. On the other hand, all of the reference memory cells
5
j are set to ‘1.”
Next, an operation is described below.
In the conventional ROM, for example, it is assumed that a memory cell
1
1,1
is set to “0” and memory cells
1
1,2
to
1
1,n
are set to “1,” respectively.
If a level “L” is given to selection signals SL
1
and SLr to select the column line CL
1
and the reference column line CLr and the word line WL
1
is selected to give a level “H,” the memory cell
1
1,1
is read out to the bit line BL and the reference memory cell
5
1
is to the reference bit line BLr, respectively. As the memory cell
1
1,1
is set to “0,” no current flows through the memory cell
1
1,1.
In addition, memory cells
1
1,2
to
1
1,n
connected in parallel between the column line CL
1
and the ground potential GND are set off since they are not selected, and therefore the electric potential of the bit line BL is substantially equal to the power supply potential VCC.
On the other hand, all of the reference memory cells
5
1
to
5
n
are set to “1” and therefore the reference memory cell
5
1
selected by the word line WL
1
is set on and other non-selected reference memory cells
5
2
to
5
n
are set off. Therefore, an electric potential of the reference bit line BLr is substantially equal to an electric potential obtained by dividing the power supply potential VCC by “on” resistance of the PMOS transistors
8
and
6
and of the reference memory cell
5
1
. An electric potential difference between the bit line BL and the reference bit line BLr is amplified by the sense amplifier
9
. In the case the electric potential of the bit line BL is higher than that of the reference bit line BLr, and therefore a content of the selected memory cell
1
1,1
is judged to be “0” and an output signal Q of “L” is output from the sense amplifier
9
.
Next, if a word line WL
2
is selected and “H” is given, the memory cell
1
1,2
is read out to the bit line BL and the reference memory cell
5
2
is to the reference bit line BLr, respectively. The memory cell
1
1,2
is set to “1” and therefore the memory cell
1
1,2
is set on. Other memory cells
1
1,3
to
1
1,n
connected in parallel between the column line CL
1
and the ground potential GND, which are not selected, are set off. Accordingly, the electric potential of the bit line BL is substantially equal to an electric potential obtained by dividing the power supply potential VCC by “on” resistance of the PMOS transistors
4
and
2
1
and of the memory cell
1
1,2
.
On the other hand, the electric potential of the reference bit line BLr is substantially equal to an electric potential obtained by dividing the power supply potential VCC by “on” resistance of the PMOS transistors
8
and
6
and of the reference memory cell
5
2
. In the case the electric potential of the bit line BL is substantially equal to that of the reference bit line BLr, and therefore a content of the selected memory cell
1
1,1
is judged to be “1” by the sense amplifier
9
and an output signal Q of “H” is output.
There is, however, a problem as described below in the conventional ROM.
Memory cells
1
i,1
to
1
i,n
are connected in parallel between the column line CLi and the ground potential GND. At an read operation, only a single memory cell
1
i,j
selected according to a word line WLj is set on and other memory cells are set off. Since each memory cell
1
i,j
is formed by an NMOS transistor, “off” resistance in an off condition is extremely high compared with “on” resistance in an on condition, though it is impossible to generate a completely non-conducting state to remove leak current in an off condition (which is referred to as “off leak current”).
Accordingly, there has been such a problem that if there are a great number of (for example, 1024) memory cells
1
i,1
to
1
i,n
connected in parallel, off leak current flowing through these memory cells totals up to a value equivalent to current flowing through the memory cell in an on condition, by which it becomes hard to judge an electric potential difference by using the sense amplifier
9
. Particularly in a mass storage ROM having a micro-structure, ratios of the “off” resistance and the “on” resistance are decreased by an application of a low voltage, which also causes a problem that an appropriate ROM cannot be designed.
According to the invention, there is provided a ROM capable of resolving these problems of the prior art as described above by eliminating effects of off leak current of non-selected memory cells to prevent a read error even if it is a large scale ROM.
SUMMARY OF THE INVENTION
It is an object of the present invention to prevent a read error by decreasing effects of leak current. To achieve the object, a read only memory having a typical constitution of the present invention comprises word lines activated in response to an address signal, sense lines inters
Mai Son
Oki Electric Industry Co. Ltd.
Volentine & Francos, PLLC
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