Communications: electrical – Digital comparator systems
Patent
1973-09-24
1976-01-20
Shaw, Gareth D.
Communications: electrical
Digital comparator systems
3401725, 340173SP, G11C 1300
Patent
active
039342336
ABSTRACT:
A read-only-memory for use in an electronic calculator or the like, implemented in a large-scale-integrated MOS semiconductor chip. The ROM is designed to save area on the chip by employing a virtual ground feature and conserve power by a precharge system. The memory cells are in an array defining X and Y lines, with the presence or absence of a bit being determined by thin oxide under an X line between adjacent Y lines. Ground lines are provided for groups of Y lines, and the Y-decode matrix includes an arrangement for connecting a selected Y-line to a non-adjacent ground line. Only the X decode section is precharged rather than all the X lines. The entire decode and read out is accomplished in a small part of the instruction cycle of the calculator.
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Fisher Roger J.
Rogers Gerald D.
Connors, Jr. Edward J.
Graham John G.
Levine Harold
Sachs Michael C.
Shaw Gareth D.
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