Read-only memory device and related method of design

Static information storage and retrieval – Read only systems

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C365S104000

Reexamination Certificate

active

07623367

ABSTRACT:
A ROM comprises several bit output lines and X address decode lines, and stores a data set. Each address decode line stores a unique data word. Addresses in the data set that have the same data word are mapped by the decoder to the same address decode line. Each address decode line is electrically connected to a bit output line as determined by the data set. An initial design of the ROM uses N connecting devices to respectively electrically connect N of the address decode lines to a bit output line. If N exceeds X/2, then an optimization process is performed. The optimization process involves electrically disconnecting each address decode line that was connected to the bit output line, and electrically connecting each address decode line that was not connected to the bit output line. The output of the bit output line is then run through a logical inverter to provide the correct output data bit.

REFERENCES:
patent: 4144561 (1979-03-01), Tu et al.
patent: 4240151 (1980-12-01), Kawagoe
patent: 4242752 (1980-12-01), Herkert
patent: 4389705 (1983-06-01), Sheppard
patent: 4402043 (1983-08-01), Guttag et al.
patent: 4419741 (1983-12-01), Stewart et al.
patent: 4571708 (1986-02-01), Davis
patent: 4716547 (1987-12-01), Baskett et al.
patent: 4831522 (1989-05-01), Henderson et al.
patent: 4888735 (1989-12-01), Lee et al.
patent: 5012451 (1991-04-01), An et al.
patent: 5047825 (1991-09-01), Yasaka et al.
patent: 5151876 (1992-09-01), Ikeda
patent: 5204842 (1993-04-01), Umeki
patent: 5231603 (1993-07-01), Luhramann
patent: 5337278 (1994-08-01), Cho
patent: 5347493 (1994-09-01), Pascucci
patent: 5373480 (1994-12-01), Kudou
patent: 5420818 (1995-05-01), Svejda et al.
patent: 5477490 (1995-12-01), Miyawaki et al.
patent: 5528534 (1996-06-01), Shoji
patent: 5598365 (1997-01-01), Shoji
patent: 5740108 (1998-04-01), Okubo
patent: 5768584 (1998-06-01), MacDonald et al.
patent: 5787033 (1998-07-01), Maeno
patent: 5880999 (1999-03-01), Ansel et al.
patent: 5907515 (1999-05-01), Hatakeyama
patent: 6018487 (2000-01-01), Lee et al.
patent: 6198678 (2001-03-01), Albon et al.
patent: 6221722 (2001-04-01), Lee
patent: 6282136 (2001-08-01), Sakurai et al.
patent: 6347064 (2002-02-01), Seo
patent: 6396767 (2002-05-01), Tzeng et al.
patent: 6429494 (2002-08-01), Zimmermann
patent: 6525954 (2003-02-01), Becker
patent: 6587364 (2003-07-01), Kablanian et al.
patent: 6687782 (2004-02-01), Normile
patent: 7035129 (2006-04-01), Khanuja
patent: 7075826 (2006-07-01), Lee et al.
patent: 7158439 (2007-01-01), Shionoiri et al.
patent: 7218544 (2007-05-01), Yamauchi
patent: 7290118 (2007-10-01), Smith et al.
patent: 7352604 (2008-04-01), Shionoiri et al.
patent: 2004/0179384 (2004-09-01), Miwa et al.
patent: 2005/0047266 (2005-03-01), Shionoiri et al.
patent: 2007/0195574 (2007-08-01), Mabuchi
patent: 2008/0056043 (2008-03-01), Jahnke et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Read-only memory device and related method of design does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Read-only memory device and related method of design, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Read-only memory device and related method of design will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4113649

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.