Read only memory device

Details Read only memory device Read only memory device

1990-10-26

1993-04-13

Popek, Joseph A.

Static information storage and retrieval

Read only systems

Semiconductive

365184, G11C 1712

Patent

active

052028488

ABSTRACT:
A read-only memory device includes a number of MIS transistors forming memory cells arranged in a matrix configuration to provide a NOR type memory device with high current driving capability for the memory cells. Bit lines and column lines are arranged alternately in common in each cell column so as to be used in common by adjacent memory cells in the word line extending direction. The bit lines for reading out signals from the memory cells function as the sources or drains of the MIS transistors of the memory cells, whereas the column lines for supplying the constant voltage to the memory cells function as the drains or sources of the MIS transistors of the memory cells. For column selection, there is provided a first selection switch for selecting a group consisting of a plurality of bit lines and a plurality of column lines. A second selection switch and a third selection switch are provided for selecting the bit line and the column line of the group, respectively. Since the bit lines and the column lines may be used fixedly, the second and third selection switches may be arranged with a layout allowance and, if these second and third selection switches are formed by MIS transistors similar to those of the memory cells, the direction in common with the memory cells may be the channel direction to contribute to improved circuit integration.

REFERENCES:
patent: 4151020 (1979-04-01), McElroy
patent: 4385432 (1983-05-01), Kuo et al.
patent: 5051809 (1991-09-01), Kiyohara
Session XII: High Density Memories, 1978 IEEE Int'l Solid-State Circuits Conference, ISSCC 78, Feb. 16, 1978, pp. 152-153.
High Noise Immunity Column Select/Sense Amplifier Circuit, IBM Technical Disclosure Bulletin, vol. 23, No. 6, Nov. 1980, pp. 2250-2254.
Method of Partitioning a CMOS ROM Array to Enhance Performance, IBM Technical Disclosure Bulletin, vol. 31, No. 5, Oct. 1988, pp. 304-305.
"Self-Aligned, Ion-Implanted Read-Only Memory", IBM Technical Disclosure Bulletin, vol. 23, No. 6, Nov. 1980, pp. 2245-2246.

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