Read only memory configuration to reduce capacitance effect...

Details Read only memory configuration to reduce capacitance effect... Read only memory configuration to reduce capacitance effect...

2005-03-15

2005-03-15

Nguyen, VanThu (Department: 2824)

Static information storage and retrieval

Read only systems

C365S185020, C365S185050, C365S185110, C365S185130, C365S185170, C365S103000

Reexamination Certificate

active

06867995

ABSTRACT:
A read only memory device includes multiple word lines, a first and second main bit line GL (n) and BL (n), sub-bit lines SB1(n) to SB4(n), selection switches MB1(n) to MB4(n), and memory cells M1(n) to M4(n). The memory cells M1(n) to M4(n) are electrically coupled to the sub-bit lines SB1(n) to SB4(n) and the sub-bit line SB1(n+1), respectively. When the memory cell M3(n) which is connected to SB3(n) is read, the sub-bit lines SB1(n) to SB3(n) are connected to the corresponding main bit lines through the turned selection switches. At this time, the sub-bit lines SB1(n) to SB3(n) are not floating but are all at the same high voltage level. Therefore, the capacitance effect will not exist between them to change the voltage level of the sub-bit lines quickly.

REFERENCES:
patent: 5341337 (1994-08-01), Hotta
patent: 6278649 (2001-08-01), Lee et al.
patent: 6577536 (2003-06-01), Chung et al.

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