Read-only memory architecture

Details Read-only memory architecture Read-only memory architecture

2005-04-12

2005-04-12

Lam, David (Department: 2818)

Static information storage and retrieval

Read only systems

Semiconductive

C365S094000, C365S177000

Reexamination Certificate

active

06879509

ABSTRACT:
The present invention provides a read-only memory (ROM) architecture. An exemplary ROM array includes a plurality of columns, a plurality of rows, a first plurality of transistors or other switches representing a “0” data state or low voltage state, and a second plurality of transistors or other switches representing a “1” data state or high voltage state. Each transistor has a corresponding drain coupled to a column and a gate coupled to a row. Each transistor of the first plurality has a source coupled to a source voltage bus, and each transistor of the second plurality has a source not coupled to the source voltage bus, through use of a programmable contact window during fabrication. In various embodiments, for a selected column, drains of pair-wise adjacent transistors share a common drain-column contact and common diffusion region.

REFERENCES:
patent: 4064493 (1977-12-01), Davis
patent: 5027319 (1991-06-01), Lai
patent: 5757690 (1998-05-01), McMahon

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