Read only memory

Details Read only memory Read only memory

1994-01-18

1994-12-13

Fears, Terrell W.

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

36518905, 36523001, 36523003, G11C 1300

Patent

active

053734807

ABSTRACT:
A read only memory includes a memory cell matrix, a word line decoder, a column decoder, and an output buffer. Said memory cell matrix is comprised of a plurality of submatrices, each of which is formed by dividing bit lines into a plurality of parts. Each sub-matrix contains the same word lines. Said word line decoder produces a signal to select a certain sub-matrix in addition to signals to select a certain word line. Said column decoder produces signals to select one column from each of said sub-matrix. Said output buffer has a column selection circuit having a plurality of stages. The first stage selects one column from each of said sub-matrices according to said signals from said column decoder. The second stage selects one column among said selected columns according to said signal to select a certain sub-matrix produced in said word line decoder. Thus, a particular memory cell is selected from the memory cell matrix. In this case, the number of memory cell transistors connected to each bit line is greatly reduced. The data readout speed of this ROM is, therefore, greatly improved in this invention.

REFERENCES:
patent: 5305282 (1994-04-01), Choi

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