Read only memory

Details Read only memory Read only memory

2002-07-16

2004-05-18

Phan, Trong (Department: 2818)

Static information storage and retrieval

Read only systems

C365S104000, C365S203000

Reexamination Certificate

active

06738280

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a technology pertaining to a bit line precharge-type semiconductor read only memory.
2. Description of the Related Art
Conventionally, a bit line precharge-type read only memory has been used in which data are stored according to whether or not there is a transistor connected to a bit line and the stored data are read out by detecting the potential of the bit line that has been precharged. Specifically, this type of read only memory has such a configuration as shown in FIG.
9
.
As seen in the figure, precharge transistors Tr
810
to Tr
8
n
0
, which constitutes a precharge circuit, are so configured as to precharge bit lines B
810
to B
8
n
0
under the control of a precharge signal
800
.
Word lines W
801
to W
80
m are respectively connected to the gates of N-channel MOS transistors Tr
811
to Tr
8
nm, which constitute columns of transistors. More specifically, for example, the word line W
801
is connected to the gates of the N-channel MOS transistors Tr
811
to Tr
8
n
1
, the word line W
802
is connected to the gates of the N-channel MOS transistors Tr
812
to Tr
8
n
2
, and the word line W
80
m is connected to the gates of the N-channel MOS transistors Tr
81
m to Tr
8
nm.
The sources of the N-channel MOS transistors Tr
811
, etc. are grounded, whereas the drains are either connected to or cut off from the corresponding bit lines B
810
to B
8
n
0
according to the data (“0” or “1”) to be recorded, Specifically, in the example shown in the figure, drains of N-channel MOS transistors Tr
811
, etc. are connected to the bit lines B
110
, etc. in the cases where data to be recorded are “0”. Accordingly, when these N-channel MOS transistors, Tr
811
, etc. are tuned ON during read-out, the potentials of the bit lines B
810
, etc. to which the drains of the N-channel MOS transistors Tr
811
, etc. are connected are changed to a low level (“L” level).
P-channel MOS transistors Tr
911
to Tr
9
n
1
constitute pull-up circuits, and the drive capability of each of these P-channel MOS transistors is determined so that when data “1” is read out (i.e., when the drains of the N-channel MOS transistors Tr
812
, etc. that are turned ON are not connected to the bit lines B
810
, etc.), the potentials of the bit lines B
810
to B
8
n
0
are maintained at a high level (“H” level), and that the drive capability is less than that of the N-channel MOS transistors Tr
811
, etc.
The bit lines B
810
to B
8
n
0
are respectively connected to inverter circuits Inv
811
and Inv
812
to Inv
8
n
1
and Inv
8
n
2
, which constitute output circuits.
In the read only memory as described above, data are read out according to the following operation.
(1) First, as shown in
FIG. 10
, the precharge signal
800
is reduced to an “L” level, the precharge transistors Tr
810
, etc. are switched to an ON state, and each of the bit lines B
810
are precharged to an “1” level.
(2) Thereafter, in response to an input address signal (not shown), one of the word lines W
801
, etc. is selected and turns to an “H” level.
(3) Then, for example, when the word line W
802
is selected and turns to an “H” level, the N-channel MOS transistors Tr
812
to Tr
8
n
2
that are connected to the word line W
802
are switched to an ON state.
In this case, the drain of the N-channel MOS transistor Tr
812
that is switched to an ON state is not connected to the bit line B
810
, and therefore, the potential of the bit line B
810
is maintained at the “H” level by the P-channel MOS transistor Tr
911
even after the precharge signal
800
has changed to the “H” level. Thus, a data “1” is output via the inverter circuits Inv
811
and Inv
812
.
Meanwhile, the drain of the N-channel MOS transistor Tr
822
that is also switched to an ON state is connected to the bit line B
820
and, in addition, the drive capability of the P-channel MOS transistor Tr
921
is made lower than the N-channel MOS transistor Tr
822
, as mentioned above. Therefore, the bit line B
810
is discharged and the potential is reduced to an “L” level. Thus, a data “0” is output via the inverter Inv
821
and Inb
822
.
In recent years, miniaturization has advanced in the process for CMOS semiconductor integrated circuit, and the power supply voltage has been more and more scaled as the thickness of the gate oxide film reduces. In order to avoid a operating speed reduction caused by the decrease of power supply voltage, there has been a trend toward reduction in threshold voltages of MOS transistors.
When the threshold voltage is reduced, however, the off leakage current of a MOS transistor increases. Consequently, in read only memories in which a number of drain nodes are connected to bit lines, the potentials of the bit lines tend to fluctuate, often causing device malfunctions. For example, in read only memories, the number of N-channel MOS transistors that are connected to bit lines often exceeds 1000, and therefore, even if the leakage current of each transistor is small, the total of the leakage current well exceeds a negligible level and affects circuit operation to cause malfunctions.
More specifically, assuming a case, for example, where there are a large number of the N-channel MOS transistors Tr
811
, etc. whose drains are connected to the bit line
810
(i.e., a case where many data “0”s are written), when the word line W
802
turns to an “H” level as described above, then the potential of the bit line B
810
cannot be maintained at the “H” level, as shown by the dashed line in FIG.
10
and results in an output data “0”, when the total of the off leakage currents of the N-channel MOS transistors Tr
811
to Tr
81
m (except Tr
812
) exceeds the current that the pull-up circuit can supply (i.e., exceeds the drive capability), even though the drain of the N-channel MOS transistor Tr
812
is not connected to the bit line B
810
(i.e., even though a data “1” has been written therein). This phenomenon is apt to occur particularly at high temperatures, at which the off leakage current increases.
On the other hand, if the drive capability of the pull-up circuit is increased to prevent such a malfunction as described above, the discharge operation by the N-channel MOS transistor Tr
822
is hindered by the pull-up circuit in the bit line B
820
, which is supposed to output a data “0,” and a time lag until the bit line B
820
reaches the “L” level becomes long as shown by the dash-dot line in FIG.
9
. This causes an increase in access time during read-out.
Moreover, as the potential of the bit line B
820
is reduced by discharging, the voltage between the source and the drain of the P-channel MOS transistor Tr
921
(pull-up circuit) increases, thereby increasing the current supplied to the bit line B
820
. As a result, the potential of the bit line B
820
cannot be reduced below the threshold level of the inverter circuit Inv
821
, further increasing the possibility of malfunctions.
SUMMARY OF THE INVENTION
In view of the foregoing and other problems, it is an object of the present invention to reliably prevent malfunctions of read only memories caused by, for example, off leakage current of transistors without increasing access time.
This and other objects are accomplished, in accordance with a first aspect of the present invention, by providing a read only memory having a plurality of bit lines, a plurality of word lines, and a plurality of switching elements, wherein data corresponding to the presence or absence of switching elements connected to the bit lines are read out by discharging electric charge precharged in the bit lines with the switching elements selected by the word lines, the read only memory comprising: at least one current supplying circuit that supplies current to one of the bit lines when the switching elements are selected by the word lines; wherein the current supplying capability of the current supplying circuit is determined according to the number of the switching elements connected to the one of the bit lines.
With this configuration, the off leakage current of

Affiliated with

Also associated with

Rating

Read only memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Read only memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Read only memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3252817