Read only memory

Details Read only memory Read only memory

1976-02-13

1977-11-08

Fears, Terrell W.

Static information storage and retrieval

Read only systems

Semiconductive

340173SP, 307238, 307279, 307317R, 365183, G11C 1140

Patent

active

040577872

ABSTRACT:
An FET read only memory array having bit locations arranged in rows and columns utilizes a dynamic array and static sensing. A dynamic first address selects the gate line of a selected column and a second address selects the source line or lines to select one or more bits within the selected column. The presence or absence of a gate at a selected bit location determines whether a first or second logic level is present at the sense or drain line serving the bit location. An additional column of FET bit positions each with a gate has the gate line activated toward the conclusion of the cycle to provide a path to ground for the elimination of any charge on a sense line in preparation for the next succeeding cycle. The sensed output from a selected bit location is latched until reset.

REFERENCES:
patent: 3529299 (1970-09-01), Chung
patent: 3611437 (1971-10-01), Varadi
patent: 3614750 (1971-10-01), Janning
patent: 3728696 (1973-06-01), Pockinghorn
patent: 3744036 (1973-07-01), Frohmann et al.

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