Read-modify-write memory using read-or-write banks

Details Read-modify-write memory using read-or-write banks Read-modify-write memory using read-or-write banks

2007-06-26

2007-06-26

Phung, Anh (Department: 2824)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S189020, C365S189070, C365S230060

Reexamination Certificate

active

10942227

ABSTRACT:
Minimal memory access times are realized by using a single access to a read-modify-write bank. read-modify-write memory including at least one read-or-write bank is operated in a manner that uses at most one access to each of the at least one read-or-write banks for each read-modify-write access to the memory during a memory cycle. The access can be effected during a single clock cycle and can be used for read, write and read-modify-write memory access.

REFERENCES:
patent: 3918033 (1975-11-01), Case et al.
patent: 3986177 (1976-10-01), Picquendar et al.
patent: 4090254 (1978-05-01), Ho et al.
patent: 4146902 (1979-03-01), Tanimoto et al.
patent: 4590589 (1986-05-01), Gerzberg
patent: 4612448 (1986-09-01), Strack
patent: 4677455 (1987-06-01), Okajima
patent: 4740922 (1988-04-01), Ogawa
patent: 4959703 (1990-09-01), Ogura et al.
patent: 5321285 (1994-06-01), Lee et al.
patent: 5324966 (1994-06-01), Muraoka et al.
patent: 5381363 (1995-01-01), Bazes
patent: 5390145 (1995-02-01), Nakasha et al.
patent: 5396454 (1995-03-01), Nowak
patent: 5412598 (1995-05-01), Shulman
patent: 5464994 (1995-11-01), Shinohe et al.
patent: 5471419 (1995-11-01), Sankaranarayanan et al.
patent: 5525820 (1996-06-01), Furuyama
patent: 5543652 (1996-08-01), Ikeda et al.
patent: 5587944 (1996-12-01), Shen et al.
patent: 5629894 (1997-05-01), Cho et al.
patent: 5689458 (1997-11-01), Kuriyama
patent: 5874751 (1999-02-01), Iwamuro et al.
patent: 5910738 (1999-06-01), Shinohe et al.
patent: 5914503 (1999-06-01), Iwamuro et al.
patent: 5936267 (1999-08-01), Iwamuro
patent: 5939736 (1999-08-01), Takahashi
patent: 5981984 (1999-11-01), Iwaana et al.
patent: 6229161 (2001-05-01), Nemati et al.
patent: 2110326 (1972-06-01), None
patent: 57 208177 (1982-12-01), None
F. Nemati and J.D. Plummer, A Novel High Density, Low Voltage SRAM Cell with a Vertical NDR Device, Center for Integrated Systems, Stanford University, Stanford, CA 94305, Jun. 1998.
F. Nemati and J.D. Plummer, A Novel Thyristor-based SRAM Cell (T-RAM) for High-Speed, Low-Voltage, Giga-scale Memories, Center for Integrated Sy stems, Stanford University, Stanford, CA, 1999.
F. Nemati and J.D. Plummer, A Novel Vertical Storage SRAM Cell, Student Paper written fro Center for Integrated Systems, Stanford University, Stanford, CA 94305.
Baliga, B. Jayant, Modern Power Devices, pp. 349-350, 1987.
Plummer, James D. and Scharf, Brad W., Insulated-Gate Planner Thyristors: I-Structure and Basic Operation, pp. 380-386, Feb. 1980.
S.M. Sze, Physics of Semiconductor Devices Second Edition, John Wiley & Sons, pp. 198-209, 1981.

Affiliated with

Also associated with

Rating

Read-modify-write memory using read-or-write banks does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Read-modify-write memory using read-or-write banks, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Read-modify-write memory using read-or-write banks will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3847528