Read FIFO scheduling for multiple streams while maintaining...

Data processing: structural design – modeling – simulation – and em – Emulation

Reexamination Certificate

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Details

C703S025000, C703S026000, C341S050000, C341S051000, C714S045000

Reexamination Certificate

active

07457739

ABSTRACT:
A method of scheduling trace packets in an integrated circuit generating trace packets of plural types stores trace data in respective first-in-first-out buffers. If a timing trace data first-in-first-out buffer is empty, timing trace data packet is transmitted. If a program counter overall data first-in-first-out buffer is not empty and the processor is at a data interruptible boundary, a program counter data packet is transmitted. If data first-in-first-out buffer is not empty, a data packet is transmitted. The program counter data packets include program counter sync data, program counter exception data, program counter relative branch data and program counter absolute branch data.

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ARM,Trace Debug Tools User Guide Version1.2, Version 1.2, 2000.

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