Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2002-10-22
2004-03-16
Auduong, Gene (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185090, C365S185230
Reexamination Certificate
active
06707714
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a flash memory, which is a nonvolatile memory, and more particularly to a read disturb alleviated NAND-type flash memory.
2. Description of the Related Art
Semiconductor nonvolatile memory is capable of storing data even when the power supply is turned off, and is widely utilized in mobile information terminals, mobile telephones, and the like. Semiconductor nonvolatile memory includes NOR-type and NAND-type flash memory, and of these, NAND-type flash memory is high-capacity memory in widespread use.
With conventional NAND-type flash memory, a plurality of segments are connected to bit lines, and each of the segments comprises a plurality of memory cells which are connected to form vertical rows. Further, segments selected by segment select signals are connected to bit lines to become the objects of read and write operations. A plurality of segments, which is connected to the bit lines by means of these segment select signals, constitutes a memory cell block. Segment select signals are therefore memory cell block select signals.
Further, within a selected memory cell block, during a read operation, a high voltage is applied to non-selected word lines within a segment such that cell transistors are controlled to assume a conductive state irrespective of stored data, and an intermediate voltage of stored data “1”, “0” is applied to selected word line within a segment such that, in accordance with stored data, selected cell transistors are controlled in a conductive or non-conductive state. For example, 0V is applied to the selected word line and 4V is applied to non-selected word lines.
Flash memory cell transistors have a constitution in which a floating gate and a control gate are formed, via an insulating layer, on a channel region between a source region and a drain region which are formed in a semiconductor substrate surface. Further, during programming, a high voltage is applied to the control gate and the drain. In accordance with the tunneling phenomenon, charge (electrons) is (are) injected into the floating gate, which makes the threshold voltage thereof high. This constitutes a programmed state (data
0
). Further, during an erase operation, a low voltage (or a negative voltage) is applied to the control gate, and a high voltage is applied to the source, such that charge is extracted from the floating gate, which makes the threshold voltage thereof low. This constitutes an erased state (data
1
).
NAND-type flash memory exhibits the problems of read disturb and over-programming. In a read disturb, since a relatively high voltage is applied to non-selected word lines within a selected block (selected segments), memory cells, which are connected to non-selected word lines, assume a light programming operation state during a read operation. As a result of being subject to such field stress, the amount of charge within the floating gate increases, which in turn raises the memory cell threshold voltage. As a result, the threshold voltage of a memory cell in an erased state (data
1
) increases, and is sometimes changed to a programmed state (data
0
). Since a NAND-type flash memory is constituted by segments, during a read operation there is a requirement to apply a high voltage to non-selected word lines which make up the majority of the word lines within a selected block. As a result, in comparison with a NOR-type flash memory, this read disturb phenomenon has a greater influence.
In order to suppress this read disturb phenomenon, the voltage applied to non-selected word lines may simply be set low. However, if the voltage of non-selected word lines is made low, this causes read problems with respect to over-programmed memory cells.
In over-programming, programming and erase operations (same are combined for a write operation) with respect to a memory cell are performed a large number of times, and this phenomenon arises upon degradation of the tunnel oxide film which lies between the drain and the floating gate of the memory cell. In other words, as a result of degradation of the tunnel oxide film, even with the same programming operation, excess electrons are applied to the floating gate such that the threshold voltage thereof becomes excessively high. This constitutes an over-programmed state.
Consequently, a memory cell, which has been frequently subjected to a write operation (programming and erasing), readily assumes an over-programmed state. Since the threshold voltage of a memory cell in an over-programmed state is high, in a read operation, if the voltage of non-selected word lines is set low, the non-selected word lines cannot be made to conduct, which in turn causes read problems.
SUMMARY OF THE INVENTION
It is accordingly an object of the present invention to provide a nonvolatile memory in which read disturb is suppressed and read problems do not arise with respect to a memory cell in an over-programmed state.
In order to resolve the above-mentioned objects, one aspect of the present invention is characterized by dividing a memory cell array of a NAND-type flash memory into a first cell array and a second cell array, and, during a read operation, applying a first voltage to non-selected word lines of the first cell array, and applying a second voltage, which is lower than the first voltage, to non-selected word lines of the second cell array. The first cell array has a comparatively large write operation frequency, and therefore readily assumes an over-programmed state as a result of repeated write operations, whereas the second cell array has a comparatively small write operation frequency, and it is therefore difficult for same to assume an over-programmed state. As a result, the voltage of non-selected word lines of the first cell array is made high, such that read problems are avoided even if over-programming arises, and the voltage of non-selected word lines of the second cell array is made low, such that a read disturb is suppressed and a data change is avoided.
A variety of methods exist for such division into a first cell array and a second cell array, namely a method for respectively allocating first and second cell arrays to: a cell array (or memory cell block), of which the address is higher than a prescribed boundary address, and a cell array (or memory cell block) of which the address is lower than the prescribed boundary address; and a method for allocating first and second cell arrays individually to a plurality of memory cell blocks. Further, by enabling this setting to be made externally, a user is then able to customize such setting.
REFERENCES:
patent: 5652450 (1997-07-01), Hirano
patent: 5872737 (1999-02-01), Tsuruda et al.
patent: 5917766 (1999-06-01), Tsuji et al.
patent: 6353555 (2002-03-01), Jeong
Arent Fox Kintner & Plotkin & Kahn, PLLC
Auduong Gene
Fujitsu Limited
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