Read concurrency through transaction synthesis

Details Read concurrency through transaction synthesis Read concurrency through transaction synthesis

1994-04-14

1996-05-28

Coleman, Eric

Boots, shoes, and leggings

364254, 3642542, 3642546, 364260, 364DIG1, G06F 1200

Patent

active

055220614

ABSTRACT:
A controller that achieves data transfer concurrency when transferring data between a CPU and a device controller by modifying the way a CPU interface within the controller transmits read access commands to a frame buffer (memory) controller connected to the interface. The interface supplies a continuous stream of read commands to the frame buffer controller after receiving the first read command from the CPU. The additional commands sent to the frame buffer controller cause it to continuously read data and send it to the interface, which stores the data in preparation for the next read command from the CPU. When the second and subsequent read requests are received by the CPU interface from the CPU, the current byte or word at the output of the FIFO within the CPU interface is returned immediately to the CPU, without having to explicitly transmit a read access command to the memory controller and wait for the resulting data.

REFERENCES:
patent: 4679038 (1987-07-01), Bantz
patent: 5315692 (1994-05-01), Hansen
patent: 5321809 (1994-06-01), Aranda
patent: 5454091 (1995-09-01), Sites

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