Read command triggered synchronization circuitry

Details Read command triggered synchronization circuitry Read command triggered synchronization circuitry

2007-06-08

2008-11-11

Le, Vu A (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S227000

Reexamination Certificate

active

07450465

ABSTRACT:
A memory READ command triggered clock synchronization mode turns on a clock synchronization circuit only for memory READ operations. The clock synchronization circuit achieves a signal lock with the reference clock signal in less time than the column address strobe latency. Precise memory READ operations are thus possible without wasting power when such operations are not performed by allowing the clock synchronization circuitry to be turned off.

REFERENCES:
patent: 6166990 (2000-12-01), Ooishi et al.
patent: 6417715 (2002-07-01), Hamamoto et al.
patent: 6677791 (2004-01-01), Okuda et al.
patent: 6754746 (2004-06-01), Leung et al.

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