Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2007-07-17
2007-07-17
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S227000
Reexamination Certificate
active
10922429
ABSTRACT:
A memory READ command triggered clock synchronization mode turns on a clock synchronization circuit only for memory READ operations. The clock synchronization circuit achieves a signal lock with the reference clock signal in less time than the column address strobe latency. Precise memory READ operations are thus possible without wasting power when such operations are not performed by allowing the clock synchronization circuitry to be turned off.
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Takanori Saeki et al., “A 2.5-ns Clock Access, 250-MHz, 256-Mb SDRAM with Synchronous Mirror Delay”, IEEE Journal of Solid-State Circuits, vol. 31, No. 11, pp. 1656-1668, Nov. 1996.
Fish & Neave IP Group Ropes & Gray LLP
Le Vu A.
Micro)n Technology, Inc.
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