Read circuit for non-volatile memories

Details Read circuit for non-volatile memories Read circuit for non-volatile memories

1998-10-29

2000-08-01

Mai, Son

Static information storage and retrieval

Floating gate

Particular biasing

3651852, G11C 1606

Patent

active

060976330

ABSTRACT:
A read circuit for non-volatile memories having an array section, with a corresponding bitline, and a reference section, with a corresponding reference bitline. A differential amplifier for comparing voltage signals obtained by current/voltage conversion of a current signal of an array cell and of a reference current signal is connected to the respective bit lines. A cascode transistor for each one of the array and reference sections, each driven by a NOR logic gate; a charge transistor for the bitline and a charge transistor for the reference bitline; column decoding transistors for the array section and for the reference section; the circuit further comprising an additional transistor which is connected between the NOR gate of the array side and a node for acquiring the array voltage sent to the differential amplifier, the additional transistor increasing the speed of the process for reading the bitline when the bitline is not charged.

REFERENCES:
patent: 5396467 (1995-03-01), Liu et al.
patent: 5717640 (1998-02-01), Hashimoto
patent: 5729492 (1998-03-01), Campardo
patent: 5757697 (1998-05-01), Briner
patent: 5901087 (1999-05-01), Pascucci
patent: 5946238 (1999-08-01), Campardo et al.

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