Read circuit for a nonvolatile memory

Details Read circuit for a nonvolatile memory Read circuit for a nonvolatile memory

2000-07-21

2001-12-04

Ho, Hoai V. (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185210

Reexamination Certificate

active

06327184

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a read circuit for a nonvolatile memory.
BACKGROUND OF THE INVENTION
As is known, in a floating gate nonvolatile memory cell, storage of a logic state is carried out by programming the threshold voltage of the cell itself through the definition of the quantity of electric charge stored in the floating gate region.
According to the information stored, memory cells may be distinguished into erased memory cells (logic state stored “1”), in which no electric charge is stored in the floating gate region, and written or programmed memory cells (logic state stored “0”), in which an electric charge is stored in the floating gate region that is sufficient to determine a sensible increase in the threshold voltage of the memory cell itself.
The most widespread method for reading nonvolatile memory cells envisages the comparison between a quantity correlated to the current flowing through the memory cell to be read and a similar quantity correlated to the current flowing through a memory cell having known contents.
In particular, to carry out reading of a memory cell, a read voltage is supplied to the gate terminal of the memory cell which has a value comprised between the threshold voltage of an erased memory cell and that of a written memory cell, in such a way that, if the memory cell is written, the read voltage is lower than the threshold voltage, and hence no current flows in the memory cell itself, whereas, if the memory cell is erased, the read voltage is higher than the threshold voltage, and hence current flows in the cell.
Reading of a memory cell is carried out by a read circuit known as “sense amplifier”, which, in addition to recognizing the logic state stored in the memory cell, also provides for the correct biasing of the drain terminal of the memory cell.
A read circuit for a nonvolatile memory is, for example, described in the European Patent Application EP-A-0814480 filed on Jun. 18, 1996 in the name of the present applicant.
According to what is illustrated in
FIG. 1
, the sense amplifier, indicated as a whole by the reference number
1
, comprises a supply line
2
set at the supply voltage V
cc
; a ground line
4
set at the ground voltage V
GND
; an array branch
6
connected, through an array bit line
8
, to a nonvolatile array memory cell
10
the contents of which it is desired to read; a reference branch
12
connected, through a reference bit line
14
, to a nonvolatile reference memory cell
16
the contents of which are known; a current-to-voltage converting stage
18
connected to the array branch
6
and reference branch
12
to convert the currents flowing in the array memory cell
10
and in the reference memory cell
16
into respective electric potentials; and a differential comparator stage
19
having the purpose of comparing these electric potentials and supplying at an output an output logic signal OUT indicative of the binary information “0” or “1” stored in the array memory cell
10
.
In particular, the array cell
10
and reference cell
16
have drain terminals receiving the same read signal V
READ
, drain terminals connected to the array bit line
8
and, respectively, to the reference bit line
14
, and source terminals connected to the ground line
4
.
The array branch
6
comprises an array column decoding block
20
connected between a node
22
(hereinafter indicated by the term “input array node
22
”) and the array bit line
8
, and is made up of three NMOS transistors
24
,
26
,
28
connected in series and receiving on gate terminals respective column decoding signals HM, HN, HO, whilst the reference branch
12
comprises a reference column decoding block
30
connected between a node
32
(hereinafter indicated by the term “input reference node
32
”) and the reference bit line
14
, and is formed of three NMOS transistors
34
,
36
,
38
connected in series, having gate terminals connected to the supply line
2
and having the purpose of setting the drain terminal of the reference memory cell
16
in the same load conditions as the drain terminal of the array memory cell
10
.
The array branch
6
and the reference branch
12
comprise an array biasing stage
40
and, respectively, a reference biasing stage
42
having the purpose of biasing at a preset potential, typically 1 V, the input array node
22
and, respectively, the input reference node
32
.
The array biasing stage
40
and the reference biasing stage
42
have an identical circuit structure and each comprise a fedback cascode structure formed of an NMOS transistor
44
and an NMOS transistor
46
, respectively, and of a regulator
48
and a regulator
50
, respectively. In particular, the NMOS transistors
44
and
46
have source terminals connected, on the one hand, to the input terminals of respective regulators
48
and
50
, and, on the other, to the array bit line
8
and, respectively, to the reference bit line
14
, drain terminals connected to the current-to-voltage converter stage
18
, and gate terminals connected to the output terminals of the respective regulators
48
,
50
.
The current-to-voltage converter stage
18
consists of a current mirror having the purpose of carrying out the above mentioned current-to-voltage conversion and comprising a first diode-connected PMOS transistor
52
arranged on the array branch
6
, and a second PMOS transistor
54
arranged on the reference branch
12
. In particular, the PMOS transistors
52
and
54
have gate terminals connected together and to the drain terminal of the PMOS transistor
52
, source and bulk terminals connected to the supply line
2
, and drain terminals connected, respectively, to the drain terminal of the NMOS transistor
44
and the drain terminal of the NMOS transistor
46
and defining respective nodes
56
,
58
, hereinafter indicated by the term “output array node
56
and output reference node
58
”.
The array branch
6
and the reference branch
12
further comprise an array precharging stage
60
and, respectively, a reference precharging stage
62
, which have the purpose of precharging the output array node
56
and, respectively, the output reference node
58
through respective current paths arranged in parallel to the current path defined by the current-to-voltage converter stage
18
.
In particular, the array precharging stage
60
and the reference precharging stage
62
are designed in such a way as to be able to supply, for the precharging of the output array node
56
and the output reference node
58
, and hence of the parasitic capacitances associated to said nodes, a much larger current than the one which, on account of their reduced size, the PMOS transistors
52
and
54
of the current-to-voltage converter stage
18
are able to supply, so enabling the precharging phase of these nodes to be speeded up considerably.
In detail, the array precharging stage
60
and the reference precharging stage
62
present an identical circuit structure and each comprise a PMOS transistor
64
and, respectively, a PMOS transistor
66
, and an NMOS transistor
68
and, respectively, an NMOS transistor
70
, having high conductivity, that is, a high W/L ratio, connected in series and arranged between the supply line
2
and the output array node
56
and, respectively, between the supply line
2
and the output reference node
58
.
In particular, the PMOS transistors
64
and
66
have source terminals and bulk terminals connected to the supply line
2
, gate terminals connected to the ground line
4
, and drain terminals connected to the drain terminal of the NMOS transistor
68
and, respectively, to the drain terminal of the NMOS transistor
70
; the said NMOS transistors
68
and
70
in turn have gate terminals receiving one and the same precharging signal SP, bulk terminals connected to the ground line
4
, and source terminals connected to the output array node
56
and, respectively, to the output reference node
58
.
The comparator stage
19
has a non-inverting input terminal connected to the output array node
56
and an invert

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