Read circuit and method for nonvolatile memory cells with an equ

Details Read circuit and method for nonvolatile memory cells with an equ Read circuit and method for nonvolatile memory cells with an equ

1997-06-18

1999-03-23

Nelms, David

Static information storage and retrieval

Floating gate

Particular biasing

3651852, G11C 1606

Patent

active

058869255

ABSTRACT:
The read circuit presents a current mirror circuit including a first and second load transistor interposed between the supply line and a respective first and second output node. The first output node is connected to a cell to be read, the second output node is connected to a generating stage generating a reference current having a predetermined characteristic, and the size of the second load transistor is N times greater than the first load transistor. To permit rapid cell reading even in the presence of low supply voltage and with no initial uncertainty, an equalizing circuit presents a current balancing branch connected between the first output node and ground for generating an equalizing current presenting a ratio of 1/N with the reference current to balance the circuit before commencing the reading.

REFERENCES:
patent: 4725984 (1988-02-01), Ip et al.
patent: 5289412 (1994-02-01), Frary et al.
patent: 5541880 (1996-07-01), Campardo
patent: 5563826 (1996-10-01), Paseucci
patent: 5594691 (1997-01-01), Bashir
patent: 5654918 (1997-08-01), Hammick
Sweha et al., "A 29ns 8MB EPROM with Dual Reference-Column ATD Sensing," in IEEE International Solid-State Circuits Conference, Digest of Technical Papers, New York, New York, Feb. 1991, pp. 264-265, 327.

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