Read bitline inhibit method and apparatus for voltage mode...

Details Read bitline inhibit method and apparatus for voltage mode... Read bitline inhibit method and apparatus for voltage mode...

2006-01-31

2006-01-31

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185030, C365S185020

Reexamination Certificate

active

06992934

ABSTRACT:
A multilevel memory system uses a source line driver circuit and a read bitline inhibit driver circuit to eliminate inhibit offset currents on unselected bitlines before memory operations of selected memory cells to equalize voltages before the operation.

REFERENCES:
patent: 5774398 (1998-06-01), Ishida
patent: 6208559 (2001-03-01), Tu et al.
patent: 6282145 (2001-08-01), Tran et al.
patent: 2005/0024956 (2005-02-01), Tran et al.

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