Read and volatile NV standby disturb

Details Read and volatile NV standby disturb Read and volatile NV standby disturb

2011-06-07

2011-06-07

Le, Vu A (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185170

Reexamination Certificate

active

07957192

ABSTRACT:
A method of operating a nonvolatile memory circuit having a plurality of transistors arranged in series between a voltage/current source node and recall sink node includes asserting a gate bias on an isolation transistor between the source node and a charge storage transistor during nonvolatile STANDBY.

REFERENCES:
patent: 5822246 (1998-10-01), Taub et al.
patent: 7244976 (2007-07-01), Cai et al.
patent: 2001/0055223 (2001-12-01), Iwahashi
patent: 2006/0104116 (2006-05-01), Yoon et al.
patent: 2007/0252192 (2007-11-01), Mokhlesi et al.
patent: 2008/0112227 (2008-05-01), Kim

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