Read and/or write integrated circuit having an operation timing

Details Read and/or write integrated circuit having an operation timing Read and/or write integrated circuit having an operation timing

1994-03-18

1995-07-18

Psitos, Aristotelis

Dynamic magnetic information storage or retrieval

General processing of a digital signal

Head amplifier circuit

360 68, G11B 59, G11B 1514

Patent

active

054347173

ABSTRACT:
A timing adjusting circuit is provided to define the operating order of a differential amplifier circuit for amplifying read-out signals and an output circuit in order to minimize changes in output DC level. A damping resistor is disposed between two magnetic head terminals and a clamp circuit in a magnetic head driving circuit. To attend to a composite head configuration, short-circuiting with a power supply and a current flowing into the magnetic head during a non-write operation are detected as abnormalities. In addition, short-circuiting and open-circuiting of the magnetic head are also detected as abnormalities. Also, a read circuit is added to a write magnetic head, in order to output read-out signals in a read mode, so that the read-out signals are utilized for detecting errors in read-out signals from an exclusively designed read head or for detecting and correcting such errors.

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David P. Swart et al, ISSCC 93/Session 13, Hard Disk and Tape Drives, Paper FA 13.4, IEEE International Solid-State Circuits Conference, 1993, pp. 218-219, 291.

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