Reactive aqueous metal oxide sols as polishing slurries for...

Details Reactive aqueous metal oxide sols as polishing slurries for... Reactive aqueous metal oxide sols as polishing slurries for...

2002-08-07

2004-04-20

Marcheschi, Michael (Department: 1755)

Abrasive tool making process, material, or composition

With inorganic material

C051S308000, C051S309000, C051S293000, C106S003000, C451S526000

Reexamination Certificate

active

06723143

ABSTRACT:

BACKGROUND
1. Field of the Invention
The present invention relates to slurries and systems utilized for chemical mechanical polishing and more particularly to chemically reactive aqueous metal oxide sol slurries and polishing systems for polishing and planarizing low dielectric constant materials, which are typically ineffectively planarized by conventional abrasive slurries.
2. Description of Related Art
Integrated circuits are typically fabricated upon a silicon wafer or substrate. For definiteness, we refer hereinafter to this substrate as a “silicon wafer” or “wafer” not intending thereby to limit the scope of the present invention. During fabrication, the surface of a silicon wafer is typically subdivided into a plurality of areas (typically rectangular) onto which are formed photolithographic images, generally identical circuit patterns from area to area. Through a series of well-known processing steps, each of the rectangular areas eventually becomes an individual die on the wafer.
Generally the integrated circuit die, especially in very large scale integrated semiconductor circuits, are manufactured by depositing and patterning a conductive layer or layers upon the semiconductor wafer and then a nonconductive layer formed from an insulator, covering the conductive layer. Present technology typically makes use of a silicon dioxide (SiO
2
) insulator, although other materials are becoming increasingly common. The layers are formed in a layered, laminar configuration, stacked upon one another creating, in general, a nonplanar topography. The non-planarity is typically caused by the nonconductive or dielectric layers being formed over raised conductive lines or other features in the underlying layer, causing topographic structure in the overlying layers. Planarization is needed for accurate deposition and patterning of subsequent layers.
As the integrated circuit devices have become more sophisticated and hence more complex, the number of layers stacked upon one another has increased. As the number of layers increase, the planarity problems generally increase as well. Planarizing the layers during the processing of the integrated circuits thus can become a major problem and a major expense in producing the circuits. The planarity requirements have resulted in a number of approaches, and most recently, chemical mechanical polishing (or “planarization”—CMP) techniques have been utilized to planarize the semiconductor wafers. CMP has been successfully included in the manufacturing process for integrated circuits since the CMP techniques are typically less complex compared to the previously utilized polishing methods. The CMP techniques typically utilize a polishing block or pad or plurality of blocks or pads in conjunction with a chemical slurry. The polishing pad (or pads) are rubbed against the layer to be planarized with the addition of a chemical slurry to aid in obtaining the planarity of the semiconductor wafer. Wafer planarity is important for accurate deposition and patterning of the wafer during further processing steps.
The necessary parameters for polishing the SiO
2
based intermetal dielectric layers are well known in the semiconductor industry. The chemical and mechanical nature of polishing and wear of the SiO
2
based dielectrics have been reasonably well developed. One problem with the SiO
2
dielectrics, however, is that the dielectric constant is relatively high, being approximately 3.9. Lower dielectric constant insulators would reduce capacitive coupling and increase processing speed. Thus, it would be highly desirable to incorporate a low dielectric constant material into semiconductor structures while still being able to utilize the conventional CMP systems for polishing the surface of the resulting dielectric material during the semiconductor wafer processing.
As the geometry of the integrated circuits continues to shrink, the intrinsic circuit delays will increase due to greater resistance in the metal interconnects and from capacitance effects from the circuit interconnects. Strategies being developed to reduce the parasitic capacitance effects include incorporating metals with lower resistivity values, such as copper, and providing electrical isolation with insulating materials having low dielectric constants relative to the SiO
2
dielectrics.
As described herein, “low dielectric constant materials” include organic polymer materials, porous dielectric materials, whether organic or inorganic, and mixed organic and inorganic materials, whether porous or not. Typically these are polymer dielectric materials which possess desirable chemical and electrical characteristics, and may include a relatively high concentration of organic materials. These low dielectric constant materials may also include relatively highly porous inorganic materials, or materials exhibiting a combination of porosity and/or organic characteristics. The low dielectric constant films can be deposited utilizing a variety of techniques including chemical vapor deposition (CVD), physical vapor deposition (PVD) and spin coating. The polymer materials generally are mechanically soft and they readily exhibit plastic deformation and hence they easily can be scratched. However, in contrast to their mechanical sensitivity, polymers are often chemically inert, being relatively unreactive towards the reagents used in conventional aqueous-based CMP. The combination of characteristics of the polymer dielectric materials makes an aqueous based polymer CMP process difficult in that mechanical abrasion is less effective at removing such materials. Incorporating these low dielectric constant materials into viable submicron fabrication techniques for integrated circuits will necessitate the development of robust CMP processes which applicants have discovered are not currently available utilizing the SiO
2
-based CMP processes or elsewhere.
Conventional polishing abrasives, such as SiO
2
and Al
2
O
3
, utilized for CMP and related polishing applications in the optical and disk industries are typically produced by chemical precipitation methods or by flame hydrolysis. In chemical precipitation, individual oxysalt particles are typically precipitated from aqueous solutions. The relatively coarse oxysalt particles are filtered, dried, and subsequently subjected to a thermal process called calcination which forms the final, finely divided oxide powder. Low calcination temperatures typically produce high surface area oxide powders that consist of very small particles. Increasing the calcination temperature typically reduces the surface area of the powder with a corresponding increase in particle size. The resulting oxide powder is formed of very small individual primary particles that are largely dehydrated and mechanically robust. However, upon calcination, the primary particles invariably consolidate to form larger aggregate particles and agglomerated aggregate particles.
In flame hydrolysis, chlorinated or silane precursor materials are subjected to a high temperature, oxyhydrogen flame. Upon entering the flame the precursor reacts with the hydrogen and oxygen, and is transformed into the final oxide product. The particle size, particle size distribution, and surface area of the resulting oxide powder can be controlled by varying the process temperature, the residence time in the reaction chamber, and the relative concentration of the chemical precursors. Oxide powders thus formed consist of very small, dehydrated primary particles that are strongly adhered to other primary particles in a 3-dimensional network referred to as an aggregate. These aggregates are mechanically robust and are considered irreducible, i.e., they cannot be broken down to the dimensional scale of the primary particles under normal use conditions. The aggregates themselves are often entangled with other aggregates forming agglomerates.
Conventional polishing slurries are typically derived by incorporating the agglomerated oxide powder into an aqueous suspension with mechanical agitation. Limited suspension stability is obtaine

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