Reachability-based verification of a circuit using one or...

Details Reachability-based verification of a circuit using one or... Reachability-based verification of a circuit using one or...

2007-10-09

2007-10-09

Hirl, Joseph P (Department: 2129)

Data processing: artificial intelligence

Knowledge processing system

Knowledge representation and reasoning technique

C706S046000, C706S045000

Reexamination Certificate

active

10704518

ABSTRACT:
In one embodiment, a method for reachability-based verification of a circuit using one or more multiply rooted binary decision diagrams (BDDs) includes generating a partitioned ordered BDD (POBDD) for one or more latches in the circuit and, for each POBDD, graphing a transition relation (TR) associated with the POBDD that reflects a plurality of input and state variables for the POBDD, generating two disjunctive partitions of the POBDD, comparing the two disjunctive partitions with a threshold, if the two disjunctive partitions are below the threshold, assigning the POBDD to the root of a noncube-based partitioning tree (NCPT) that comprises a plurality of leaves, and, for each leaf of the NCPT, composing one or more decomposition points and generating one or more partitions z. The method includes using each partition of the TR, performing a reachability-based analysis until one or more fixed points are reached.

REFERENCES:
patent: 5243538 (1993-09-01), Okuzawa et al.
John Lafferty, Ordered Binary Decision Diagrams and Minimal Trellises, Sep. 1999, IEEE, vol. 48, No. 9, pp. 971-973.

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