Re-triggerable monostable multivibrator capable of generating a

Details Re-triggerable monostable multivibrator capable of generating a Re-triggerable monostable multivibrator capable of generating a

1989-08-07

1992-02-04

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307265, 328207, H03K 3284

Patent

active

050862375

ABSTRACT:
A monostable multivibrator comprises an input circuit receiving an trigger signal for generating an instantaneous pulse, a timing generation circuit receiving the instantaneous pulse for generating a timing defining signal after a predetermined time, and an output circuit for generating a output pulse starting in response to the instantaneous pulse and terminating at the timing defining signal. The timing generation circuit includes a time constant circuit including at least a capacitor, an OR gate having a first input connected to receive the output signal of the output circuit, a first logic circuit operating to discharge the capacitor when an output of the OR gate is in a first level and to charge the capacitor when the output of the OR gate is in a second level opposite to the first level, a second logic circuit for generating the timing defining signal when the potential of the capacitor reaches a first predetermined reference voltage, a third logic circuit for generating a reset signal when the potential of the capacitor is higher than a second predetermined reference voltage which is higher than the first predetermined reference voltage, and a flipflop reset in response to the reset signal and driven in response to the instantaneous pulse. An output of the flipflop is connected to a second input of the OR gate. When the reset signal is not active, if the instantaneous pulse is applied to the flipflop, the output of the flipflop is brought to the first level, so as to cause the first logic circuit to forcibly discharge the capacitor of the time constant circuit. Thereafter when the reset signal becomes active, the output of the flipflop is brought to the second level, so as to cause the first logic circuit to forcibly charge the capacitor of the time constant.

REFERENCES:
patent: 4051387 (1977-09-01), Black
patent: 4965465 (1990-10-01), Denda

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