Pulse or digital communications – Miscellaneous
Reexamination Certificate
1998-12-17
2001-06-26
Bocure, Tesfaldet (Department: 2631)
Pulse or digital communications
Miscellaneous
C375S355000, C375S372000
Reexamination Certificate
active
06252919
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to sample-rate conversion in audio systems, and more particularly to dynamically adding or deleting samples to adjust the conversion ratio.
BACKGROUND OF THE INVENTION
Digital-audio systems are often found in inexpensive personal computers (PC's). Audio inputs are typically sampled at a rate of 11.025, 22.05, or 44.1 KHz, or at rates of 8, 16, 32, or 48 KHz. These audio samples are often stored and altered in a PC before being played back, often at a different rate.
It may be desired to play back an audio sample at a different rate, or to mix audio samples having different sample rates. One of the audio samples must be converted to the sample rate of the other audio sample for mixing or playback to occur. Sample-rate conversion software or hardware is used to convert the sample rate.
While many approaches to sample-rate conversion are used, satisfactory results are not always achieved. The human ear is quite sensitive to slight distortions or discontinuities of a sound. Coarse sample-rate conversion produces noticeable distortion.
A particular problem occurs when audio streams are synchronized to independent free-running clocks. The clocks for the two audio streams may be generated from two different crystal oscillators. Even when the frequencies are the same, slight differences can occur between the two crystals. The frequency difference may be up to 1000 parts-per-million (ppm). For a nominal 11,025 Hz sample rate, the frequency can be as high as 11025+11.025 or 11036 Hz. When a 11036 Hz audio signal synchronized to one crystal oscillator is converted to a 11025 Hz rate, audio samples may be deleted after every thousand or so samples. Deleting audio samples can cause audible clicks or pops.
Analog SRC—FIG.
1
FIG. 1
shows a prior-art sample-rate conversion using a pair of digital-analog converters. An input audio stream was sampled at frequency f
0
, and has samples x(0), x(1), . . . x(m). Each sample is a multi-bit binary number representing the intensity of the sound at a point in time; 16-bit binary mumbers in two's complement are commonly used for each sample. The input sample at frequency f
0
is to be converted to the output audio stream having a sample rate of f
1
, with samples y(0), y(1), . . . y(n). The number of sample points in the input stream, m, often differs from the number of samples in the output stream, n. The ratio of the number of samples, m
, is equal to the frequency ratio f
0
/f
1
. The converted audio stream must have the same total play time, even though the number of samples increases or decreases and the rate of sample play back likewise increases of decreases.
The digital input samples x(i) are converted to analog voltages on line
6
by digital-to-analog converter (DAC)
8
. DAC
8
converts an input sample for each period of input clock
16
, which operates at input frequency fO. The capacitance on line
6
maintains the voltage generated by DAC
8
until the next sample is converted.
The voltage on line
6
is sampled by analog-to-digital converter (ADC)
10
, which generates a digital value representing the voltage sampled from line
6
. This digital value is output as output sample y(i). ADC
10
samples the voltage on line
6
for each period of output clock
15
, which operates at output frequency f
1
.
While such an analog sample converter may be considered exact, since DAC
8
and ADC
10
operate from independent clocks
15
,
16
, it is complex and expensive. The analog circuits are difficult to integrate with other digital circuits on a VLSI integrated circuit (IC). Also, the quality of the digital audio stream is degraded by the multiple analog-digital conversions.
FIFO with SRC—FIGS.
2
,
3
FIG. 2
illustrates using a FIFO to buffer a sample-rate converter. First-in-first-out FIFO
12
is written with an input audio sample x(i) for each pulse of the input clock
16
, which operates at input frequency f
0
. Sample-rate converter
14
is an all-digital converter that reads digital samples from FIFO
12
and outputs digital samples at the output frequency f
1
in response to output clock
15
. Sample-rate converter
14
generates derived clock
18
from output clock
15
by multiplying the output clock by Q and dividing by P. Thus derived clock
18
has a derived frequency f
2
of (Q/P)*f
1
. Q and P are chosen so that f
2
is about the same as input frequency f
0
. Thus FIFO
12
is read and written at about the same frequency.
When Q/P is not exactly the ratio of f
0
to f
1
, FIFO
12
is read and written at slightly different rates. FIFO
12
can fill up or become empty. Samples can over-write earlier samples, or random or null data can be output as a sample. Thus simply using a FIFO can produce undesirable audio noise.
FIG. 3
shows using read and write pointers to control the FIFO buffering a sample-rate converter. Write counter
24
is clocked by input clock
16
while read counter
26
is clocked by derived clock
18
. Thus write counter
24
keeps track of the write location in FIFO
12
while read counter
26
indicates the reading location in FIFO
12
. Comparator
28
compares the values of write counter
24
and read counter
26
to determine when FIFO
12
is full or empty.
When write counter
24
matches read counter
26
, FIFO
12
has become empty, and signal
30
causes FIFO
12
to continue to output the last audio sample, effectively duplicating an audio sample. When write counter
24
is ahead of read counter
26
by the size of FIFO
12
, then comparator
28
detects that FIFO
12
is full. Input samples are prevented from being written into FIFO
12
until one or more samples have been read out to sample-rate converter
14
. This essentially drops an audio sample.
Audible distortions can occur when FIFO
12
fills, since an input sample must be skipped rather than written to the full FIFO. When FIFO
12
becomes empty, a sample is missing and a previous sample may need to be duplicated, or a null or random sample output. While this is superior to simply allowing FIFO
12
to over-run or under-run, audible clicks or pops may still be discernable by the listener. Noise can occur when samples are abruptly added or deleted.
What is desired is a digital sample-rate converter for common PC-audio sampling rates. It is desired to buffer digital-audio samples synchronized to independent clocks that may vary slightly in frequency. A digital sample-rate converter is desired that can eliminate audible clicks and pops caused by slight mismatches of sampling rates. A sample-rate converter that adds or removes samples without audible distortion is also desirable. High audio quality is desirable when samples from independent crystal oscillators are used.
SUMMARY OF THE INVENTION
A sample-rate converter has an input stream of samples representing audio intensities at points in time. The input stream is for playing the samples at an input rate of an input clock. An output stream of samples represent audio intensities at points in time. The output stream is for playing the samples at an output rate of an output clock. A buffer receives the samples from the input stream in response to the input clock.
A derived-clock generator is coupled to the output clock. It generates a derived clock from the output clock. The buffer outputs samples in response to the derived clock to form a buffered stream. A delay register is coupled to the buffer. It delays samples in the buffered stream by a period of the derived clock. The delay register outputs a delayed stream.
A fade-in generator is coupled to the buffer and to the delay register. It fades in the delayed stream by gradually inserting an extra sample into a faded stream of samples by gradually increasing a weighting of samples from the delayed stream and gradually decreasing a weighting of samples from the buffered stream, the fade-in generator outputting the faded stream.
A filter stage is coupled to receive samples in the faded stream from the fade-in generator in response to a derived clock. It converts samples read from t
Auvinen Stuart T.
Bocure Tesfaldet
NeoMagic Corp.
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